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參數(shù)資料
型號: MK20DN512ZVLQ10
廠商: Freescale Semiconductor
文件頁數(shù): 8/75頁
文件大?。?/td> 0K
描述: IC ARM CORTEX MCU 512KB 144LQFP
標準包裝: 300
系列: Kinetis
核心處理器: ARM? Cortex?-M4
芯體尺寸: 32-位
速度: 100MHz
連通性: CAN,EBI/EMI,I²C,IrDA,SDHC,SPI,UART/USART,USB,USB OTG
外圍設備: DMA,I²S,LVD,POR,PWM,WDT
輸入/輸出數(shù): 100
程序存儲器容量: 512KB(512K x 8)
程序存儲器類型: 閃存
RAM 容量: 128K x 8
電壓 - 電源 (Vcc/Vdd): 1.71 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 33x16b,D/A 2x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 144-LQFP
包裝: 托盤
Table 4. Voltage and current operating behaviors (continued)
Symbol
Description
Min.
Typ.1
Max.
Unit
Notes
IIND
Input leakage current, digital pins
VDD < VIN < 5.5 V
1
50
μA
4, 5
ZIND
Input impedance examples, digital pins
VDD = 3.6 V
VDD = 3.0 V
VDD = 2.5 V
VDD = 1.7 V
48
55
57
85
4, 7
RPU
Internal pullup resistors
20
35
50
RPD
Internal pulldown resistors
20
35
50
1. Typical values characterized at 25°C and VDD = 3.6 V unless otherwise noted.
2. Open drain outputs must be pulled to VDD.
3. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
4. Digital pins have an associated GPIO port function and have 5V tolerant inputs, except EXTAL and XTAL.
5. Internal pull-up/pull-down resistors disabled.
6. Characterized, not tested in production.
7. Examples calculated using VIL relation, VDD, and max IIND: ZIND=VIL/IIND. This is the impedance needed to pull a high
signal to a level below VIL due to leakage when VIL < VIN < VDD. These examples assume signal source low = 0 V.
8. Measured at VDD supply voltage = VDD min and Vinput = VSS
9. Measured at VDD supply voltage = VDD min and Vinput = VDD
+
Digital input
Source
Z IND
I IND
5.2.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSx→RUN recovery times in the following table
assume this clock configuration:
CPU and system clocks = 100 MHz
Bus clock = 50 MHz
FlexBus clock = 50 MHz
Flash clock = 25 MHz
MCG mode: FEI
General
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
16
Freescale Semiconductor, Inc.
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