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參數(shù)資料
| 型號： | MK2059-01SILF |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 25.92 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| 封裝： | 0.300 INCH, ROHS COMPLIANT, SOIC-20 |
| 文件頁數(shù)： | 4/10頁 |
| 文件大?。?/td> | 184K |
| 代理商： | MK2059-01SILF |
VCXO-Based Frame Clock Frequency Translator
MDS 2059-01 F
3
Revision 030106
Integrated Circuit Systems, Inc.
● 525 Race Street, San Jose, CA 95126 ● tel (408) 295-9800 ● www.icst.com
MK2059-01
Functional Description
The MK2059-01 is a clock generator IC that generates
an output clock directly from an internal VCXO circuit
which works in conjunction with an external quartz
crystal. The VCXO is controlled by an internal PLL
(Phase Locked Loop) circuit, enabling the device to
perform clock regeneration from an input reference
clock. The MK2059-01 is configured to provide a MHz
communications reference clock output from an 8kHz
input clock. There are 12 selectable output frequencies.
Please refer to the Output Clock Selection Table on
Page 2.
Most typical PLL clock devices use an internal VCO
(Voltage Controlled Oscillator) for output clock
generation. By using a VCXO with an external crystal,
the MK2059-01 is able to generate a low jitter, low
phase-noise output clock within a low bandwidth PLL.
This serves to provide input clock jitter attenuation and
enables stable operation with a low frequency
reference clock.
The VCXO circuit requires an external pullable crystal
for operation. External loop filter components enable a
PLL configuration with low loop bandwidth.
Application Information
Output Frequency Configuration
The MK2059-01 is configured to generate a set of
output frequencies from an 8kHz input clock. Please
refer to the Output Clock Selection Table on Page 2.
Input bits SEL2:0 are set according to this table, as is
the external crystal frequency. Please refer to the
Quartz Crystal section on this page regarding external
crystal requirements.
Input Mux
The Input Mux serves to select between two alternate
input reference clocks. Upon reselection of the input
clock, clock glitches on the output clock will not be
generated due to the “fly-wheel” effect of the VCXO
(the quartz crystal is a high-Q tuned circuit). When the
input clocks are not phase aligned, the phase of the
output clock will change to reflect the phase of newly
selected input at a controlled phase slope (rate of
phase change) as influenced by the PLL loop
characteristics.
Quartz Crystal
It is important that the correct type of quartz crystal is
used with the MK2059-01. Failure to do so may result in
reduced frequency pullability range, inability of the loop
to lock, or excessive output phase jitter.
The MK2059-01 operates by phase-locking the VCXO
circuit to the input signal of the selected ICLK input.
The VCXO consists of the external crystal and the
integrated VCXO oscillator circuit. To achieve the best
performance and reliability, a crystal device with the
recommended parameters (shown below) must be
used, and the layout guidelines discussed in the PCB
Layout Recommendations section must be followed.
The frequency of oscillation of a quartz crystal is
determined by its cut and by the external load
capacitance. The MK2059-01 incorporates variable
load capacitors on-chip which “pull”, or change, the
frequency of the crystal. The crystals specified for use
with the MK2059-01 are designed to have zero
frequency error when the total of on-chip + stray
capacitance is 14pF. To achieve this, the layout should
use short traces between the MK2059-01 and the
crystal.
PLL Loop Filter Components
All analog PLL circuits use a loop filter to establish
operating stability. The MK2059-01 uses external loop
filter components for the following reasons:
1) Larger loop filter capacitor values can be used,
allowing a lower loop bandwidth. This enables the use
of lower input clock reference frequencies and also
input clock jitter attenuation capabilities. Larger loop
filter capacitors also allow higher loop damping factors
when less passband peaking is desired.
2) The loop filter values can be user selected to
optimize loop response characteristics for a given
application.
Referencing the External Component Schematic on
this page, the external loop filter is made up of
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK2059-01SILFTR | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 VCXO-BASED FRAME CLK FREQUENCY TRANSLATOR RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MK2059-01SITR | 功能描述:IC VCXO CLK JITTER ATTEN 20-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MK2069-01 | 制造商:ICS 制造商全稱:ICS 功能描述:VCXO-Based Line Card Clock Synchronizer |
| MK2069-01GI | 功能描述:IC VCXO CLK SYNCHRONIZER 56TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MK2069-01GILF | 功能描述:時鐘合成器/抖動清除器 VCXO-BASED LINE CARD CLOCK SYNCHRONIZER RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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