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參數(shù)資料
| 型號(hào)： | MK2049-01SI |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 44.736 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| 封裝： | 0.300 INCH, SOIC-20 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 125K |
| 代理商： | MK2049-01SI |
MK2049-01
Communications Clock PLL
MDS 2049-01 K
2
Revision 091801
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA 95126 (408)295-9800tel www.icst.com
Number
Name
Type Description
1
FS1
I
Frequency Select 1. Determines CLK input/outputs per tables above.
2
X2
O
Crystal conection. Connect to a 12.288 MHz or 12.96 MHz crystal.
3
X1
I
Crystal conection. Connect to a 12.288 MHz or 12.96 MHz crystal.
4
VDD
P
Connect to +5V.
5
VDD
P
Connect to +5V.
6
VDD
P
Connect to +5V.
7
GND
P
Connect to ground.
8
CLK2
O
Clock 2 output determined by status of FS3:0 per tables above.
9
CLK1
O
Clock 1 output determined by status of FS3:0 per tables above. CLK2 divided by 2.
10
8K
O
Recovered 8 kHz clock output. On External mode only.
11
FS2
I
Frequency Select 2. Determines CLK input/outputs per tables above.
12
FS3
I
Frequency Select 3. Determines CLK input/outputs per tables above.
13
ICLK
I
Input clock connection. Connect to 8 kHz backplane or to Loop Timing clock.
14
GND
P
Connect to ground.
15
VDD
P
Connect to +5V.
16
CAP1
LF
Connect a 0.030 F ceramic capacitor and a 7.5 M
resistor in series between this pin and CAP2.
17
GND
P
Connect to ground.
18
CAP2
LF
Connect a 0.030 F ceramic capacitor and a 7.5 M
resistor in series between this pin and CAP1.
19
GND
P
Connect to ground.
20
FS0
I
Frequency Select 0. Determines CLK input/outputs per tables above.
Pin Descriptions
Type: I = Input, O = output, P = power supply connection, LF = loop filter connection
Pin Assignment
20 pin (300 mil) SOIC
1
16
2
3
4
15
14
13
VDD
GND
X2
VDD
GND
5
6
7
8
12
11
10
9
FS3
X1
FS1
FS0
CAP1
ICLK
8K
CLK1
CLK2
18
17
19
20
VDD
FS2
GND
CAP2
0 = connect directly to ground, 1 = connect directly to VDD.
Crystal is applied to pins 2 and 3; clock input is applied to pin 13.
Output Decoding Table – External Mode (MHz)
Input
FS3 FS2 FS1 FS0
CLK1
CLK2
Crystal
8 kHz
0
1.544
3.088
12.288
8 kHz
0
1
2.048
4.096
12.288
8 kHz
0
1
0
22.368
44.736
12.288
8 kHz
0
1
17.184
34.368
12.288
8 kHz
0
1
19.44
38.88
12.96
Input
FS3 FS2 FS1 FS0
CLK1
CLK2
Crystal
1.544
1
0
1.544
3.088
12.288
2.048
1
0
1
2.048
4.096
12.288
44.736
1
0
1
0
22.368
44.736
12.288
34.368
1
0
1
17.184
34.368
12.288
Output Decoding Table – Loop Timing Mode (MHz)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MK2049-01SILF | 44.736 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-01SILF | 44.736 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-36SILF | 155.52 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-44SILFTR | 51.84 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-44SILF | 51.84 MHz, OTHER CLOCK GENERATOR, PDSO20 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK2049-01SITR | 制造商:ICS 制造商全稱:ICS 功能描述:Communications Clock PLL |
| MK2049-01STR | 制造商:Integrated Device Technology Inc 功能描述:PLL CLOCK SYNTHESIZER SGL 20SOIC - Tape and Reel |
| MK2049-02 | 制造商:ICS 制造商全稱:ICS 功能描述:Communications Clock PLLs |
| MK2049-02S | 制造商:ICS 制造商全稱:ICS 功能描述:Communications Clock PLLs |
| MK2049-02SI | 制造商:ICS 制造商全稱:ICS 功能描述:Communications Clock PLLs |
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