參數(shù)資料
型號(hào): MK1716R-01RT
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi): 時(shí)鐘產(chǎn)生/分配
英文描述: 133.33 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28
封裝: 0.150 INCH, SSOP-28
文件頁(yè)數(shù): 3/9頁(yè)
文件大?。?/td> 217K
代理商: MK1716R-01RT
MK1716-01
SERIAL PROGRAMMABLE PCI SS VERSACLOCK SYNTHESIZER
SSCG
IDT SERIAL PROGRAMMABLE PCI SS VERSACLOCK SYNTHESIZER
3
MK1716-01
REV G 121809
Configuring the MK1716-01
Initial State: The MK1716-01 may be configured to have up to nine frequency outputs, utilizing a single PLL and
on-board spread spectrum circuitry. Unprogrammed, the part has the following outputs, related to the reference
input clock:
The STROBE pin must have an external 250 kOhm pull-up resistor to acheive the Initial State.
The input crystal range for the MK1716-01 is 5 MHz to 27 MHz.
The MK1716-01 can be programmed to set the output functions and frequencies. 160 data bits generated by the
VersaClockTM software are written in DATA pin in this order: MSB (left most bit) first.
As show in Figure 2, after these 160 bits are clocked into the MK1716-01, taking STROBE high will send this data
to the internal latch and the CLK output will lock within 10 ms.
Note: STROBE utilizes a transparent latch that is latched when in the high state. If STROBE is in the high state and
SCLK is pulsed, DATA is clocked directly to the internal latch and the output conditions will change accordingly.
Although this will not damage the MK1716-01, it is recommended that STROBE be kept low while DATA is being
clocked into the MK1716-01 in order to avoid unintended changes on the output clocks.
AC Parameters for Writing to the MK1716-01
Default Outputs
Output
Frequency
Clock 1-9 (Pins 4, 10 - 19)
Reference output
Parameter
Condition
Min.
Max.
Units
tSETUP
Setup time
10
ns
tHOLD
Hold time after SCLK
10
ns
tW
Data wait time
10
ns
tS
Strobe pulse width
40
ns
SCLK Frequency
30
MHz
DATA
t
hold
t
setup
SCLK
STROBE
t
s
t
w
Figure 2. Tim ing D iagram for Program m ing the M K1716-01
Bit160
Bit2
Bit1
Bit3
Bit159
Bit158
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