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參數(shù)資料
| 型號(hào)： | MK1704ALF |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 140 MHz, VIDEO CLOCK GENERATOR, PDSO8 |
| 封裝： | 0.150 INCH, LEAD FREE, SOIC-8 |
| 文件頁數(shù)： | 2/6頁 |
| 文件大?。?/td> | 124K |
| 代理商： | MK1704ALF |
Low EMI Clock Generator
MDS 1704A E
2
Revision 120903
Integrated Circuit Systems, Inc.
● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
MK1704A
Pin Assignment
8 pin (150 mil) SOIC
Output Clock Selection Table
Pin Descriptions
External Components
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50
trace (a
commonly used trace impedance), place a 33
resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20
.
Decoupling Capacitor
A decoupling capacitor of 0.01F must be connected
between VDD and GND on pins 2 and 3.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) The 0.01F decoupling capacitor should be mounted
on the component side of the board as close to the
VDD pin as possible. No vias should be used between
decoupling capacitor and VDD pin. The PCB trace to
VDD pin should be kept as short as possible, as should
the PCB trace to the ground via. Distance of the ferrite
bead and bulk decoupling from the device is less
critical.
2) The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
should not be routed next to each other with minimum
spaces, instead they should be separated and away
from other traces.
3) To minimize EMI the 33
series termination resistor,
if needed, should be placed close to the clock output.
ICLK
VDD
GND
S0
CLK
S1
LEE
NC
1
2
3
4
8
7
6
5
S1 S0
Input
Min.
Input
Nom.
Input
Max. Mult.
Freq.
spread
vs. CLK
0
60
135
140
x1
+0.5, -1.5%
0
1
60
80
120
x1
+0.5, -1.5%
1
0
30
40
60
x1
Down 2.5%
1
40
65
100
x1
+0.5, -1.5%
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
ICLK
XI
Connect to a clock input as shown in table above.
2
VDD
Power
Connect to +3.3V or +5V.
3
GND
Power
Connect to ground.
4
CLK
Output
Clock output equal to input frequency.
5
LEE
Input
Low EMI enable. Turns on the spread spectrum when high. Internal pull-up.
6
S1
Input
Frequency select 1 input. Selects input/output clock range per table above.
Internal pull-up.
7
S0
Input
Frequency select 0 input. Selects input/output clock range per table above.
Internal pull-up.
8
NC
-
No connect. Do not connect anything to this pin.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK1704ALFTR | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 LOW EMI CLOCK GENERATOR RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MK1704ATR | 功能描述:IC CLK GENERATOR LOW EMI 8-SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MK1705A | 功能描述:IC CLK GEN ATI LOW EMI 8-SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| MK1705ALF | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 ATI LOW EMI CLOCK GENERATOR RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MK1705ALFTR | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 ATI LOW EMI CLOCK GENERATOR RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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