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參數(shù)資料
| 型號： | MK1631-01S |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 40.5 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
| 封裝： | 0.150 INCH, SOIC-16 |
| 文件頁數(shù)： | 3/4頁 |
| 文件大?。?/td> | 43K |
| 代理商： | MK1631-01S |
MK1631
VCD with NTSC/PAL Clock Source
MDS1631B
3
Revision 12047
Printed 12/4/97
MicroClock Division of ICS1271 Parkmoor Ave.San JoseCA95126(408)295-9800tel(408)295-9818fax
ICRO
CLOCK
Parameter
Conditions
Minimum
Typical
Maximum
Units
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage, VDD
Referenced to GND
7
V
Inputs and Clock Outputs
-0.5
VDD+0.5
V
Ambient Operating Temperature
0
70
°C
Soldering Temperature
Max of 10 seconds
250
°C
Storage Temperature
-65
150
°C
DC CHARACTERISTICS
Operating Voltage, VDD
4.5
5.5
V
Input High Voltage, VIH
2
V
Input Low Voltage, VIL
0.8
V
Output High Voltage
IOH=-4mA
VDD-0.4
V
Output High Voltage
IOH=-25mA
2.4
V
Output Low Voltage
IOL=25mA
0.4
V
Operating Supply Current, IDD
No Load, VDD=5.0V
TBD
mA
Short Circuit Current
Each output
±100
mA
Input Capacitance, X1 and X2 pins
15
pF
Input Capacitance
7
pF
Actual mean frequency error versus target, note 2
13.5, 27, and 40.5MHz
1
ppm
Actual mean frequency error versus target, note 2
NTSC/PAL clocks
1
ppm
Actual mean frequency error versus target
Controller clocks
0.02
%
AC CHARACTERISTICS
Input Frequency
16.9344
MHz
Output Clock Rise Time
0.8 to 2.0V
1.5
ns
Output Clock Fall Time
2.0 to 0.8V
1.5
ns
Output Clock Duty Cycle, High Time
At VDD/2
45
49 to 51
55
%
Output Clock Duty Cycle, High Time, 35.5MHz At VDD/2
40
60
%
Absolute Clock Period Jitter
250
ps
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure
to levels above the operating limits but below the Absolute Maximums may affect device reliability.
2. Provided the crystal is properly tuned, or an accurate 16.9344 MHz input clock is used.
External Components/Crystal Selection
Electrical Specifications
The MK1631 requires a minimum number of external components for proper operation. For a crystal input,
a parallel resonant 16.9344 MHz, 16pF load, crystal is recommended. The frequency tolerance of the
crystal should be 50ppm or better. For a clock input, connect to X1 and leave X2 unconnected. Decoupling
capacitors of 0.1F must be connected between VDD and GND pins (pins 4 and 5, 13 and 11) very close
to the chip, and 33
terminating resistors should be used on clock outputs with traces longer than 1 inch.
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