參數(shù)資料
型號: MK1581-01GILFTR
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 1/11頁
文件大?。?/td> 0K
描述: IC CLK GENERATOR T1/E1 16-TSSOP
標(biāo)準(zhǔn)包裝: 2,500
類型: 時鐘發(fā)生器
PLL:
輸入: 時鐘,晶體
輸出: CMOS
電路數(shù): 1
比率 - 輸入:輸出: 2:1
差分 - 輸入:輸出: 無/無
頻率 - 最大: 2.048MHz
除法器/乘法器: 是/無
電源電壓: 3.15 V ~ 3.45 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 帶卷 (TR)
DATASHEET
LOW PHASE NOISE T1/E1 CLOCK GENERATOR
MK1581-01
IDT LOW PHASE NOISE T1/E1 CLOCK GENERATOR
1
MK1581-01
REV F 051310
Description
The MK1581-01 provides synchronization and timing
control for T1 and E1 based network access or multitrunk
telecommunication systems. The device accepts an 8 kHz
frame clock input and uses an on-chip VCXO to produce a
synchronized low phase noise clock output.
This monolithic IC, combined with an external inexpensive
quartz crystal, can be used to replace a more costly hybrid
VCXO retiming module. Through selection of external loop
filter components values, the device can be tailored to meet
the system’s clock jitter attenuation requirements. Low-pass
jitter attenuation characteristics in the Hz range are
possible.
Features
Generates a T1 (1.544 MHz) or E1 (2.048 MHz) output
clock from an 8kHz frame clock input
Configurable jitter attenuation characteristics, excellent
for use as a Stratum source de-jitter circuit
VCXO-based clock generation ensures very low jitter and
phase noise generation
Output clock is phase and frequency locked to the input
reference clock
+115ppm minimum crystal frequency pullability range,
using recommended crystal
Industrial temperature range
Low power CMOS technology
16 pin TSSOP package
Single 3.3 V power supply
Block Diagram
Charge
Pump
VCXO
Pullable Crystal
Output
Divider
Feedback
Divider
8kHz_IN
CLK
X2
X1
ISET
VDD
3
VDD
VIN
CHGP
5
GND
SEL
Phase
Detector
C
P
C
S
R
S
R
SET
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