參數(shù)資料
型號: MK1492-03RTR
元件分類: 時鐘產(chǎn)生/分配
英文描述: 75 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28
封裝: 0.150 INCH, SSOP-28
文件頁數(shù): 5/7頁
文件大小: 70K
代理商: MK1492-03RTR
MK1492-03
Intel Mobile/SDRAM Clock Source
MDS 1492-03 D
5
Revision 020298
Printed 11/15/00
MicroClock Division of ICS1271 Parkmoor Ave.San JoseCA95126(408)295-9800tel(408)295-9818fax
PRELIMINARY INFORMATION
I C R O
C LOC K
Serial Configuration Command Bitmaps
Byte 0: Functional and Frequency Select Clock Register (1 = enable, 0 = disable)
Note: PD = Power-On Default
Bit
Pin #
Description
PD
7
--
(Reserved) MSB
0
6
--
(Reserved)
0
5
--
(Reserved)
0
4
--
(Reserved) LSB
0
3
--
Not used
1
2
21
48/24 MHz (Frequency Select) 1 = 48 MHz, 0 = 24 MHz
1
--
Bit 1
Bit 0
0
1
1 - Tri-State all outputs
0
1
0 - Spread Spectrum for HOST and PCI clocks
0
1 - Normal Operation (Test Mode not supported)
0
0 - Normal Operation
Byte 1: CPU, 24/48 MHz Active/Inactive Register (1 = enable, 0 = disable)
Bit
Pin #
Name
Intel Description
7
28
F1
48/24 MHz (Active/Inactive)
6
21
48M/24M 48/24 MHz (Active/Inactive)
5
--
(Reserved)
4
N/A
--
CPUCLK4 (Active/Inactive)
3
10
HOST2 CPUCLK3 (Active/Inactive)
2
10
HOST2 CPUCLK2 (Active/Inactive)
1
8
HOST1 CPUCLK1 (Active/Inactive)
0
8
HOST1 CPUCLK0 (Active/Inactive)
Notes:
Bits 0 and 1 must always be at the same state. Bits 2 and 3 must always be at the same state.
Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable)
Bit
Pin #
Name
Intel Description
7
--
(Reserved)
6
22
PCIF
PCICLK_F (Active/Inactive)
5
N/A
--
PCICLK5 (Active/Inactive)
4
N/A
--
PCICLK4 (Active/Inactive)
3
N/A
--
PCICLK3 (Active/Inactive)
2
27
PCI
PCICLK2 (Active/Inactive)
1
25
PCI
PCICLK1 (Active/Inactive)
0
24
PCI
PCICLK0 (Active/Inactive)
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