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參數(shù)資料
| 型號(hào)： | MK1491E-14RTR |
| 英文描述： | OPTi ACPI Firestar Clock Source |
| 中文描述： | 奧普蒂ACPI的FireStar在時(shí)鐘源 |
| 文件頁(yè)數(shù)： | 2/4頁(yè) |
| 文件大?。?/td> | 69K |
| 代理商： | MK1491E-14RTR |
MK1491-14
OPTi ACPI Firestar Clock Source
MDS 1491-14 B
Integrated Circuit Systems, Inc. 525
Race Street San Jose CA 95126 (408)295-9800tel www.icst.com
2
Revision 061801
Pin Descriptions
Pin #
1, 20, 26
2
3
4, 11, 17, 23
5
6, 7, 9, 10
8
12
13
14
15
16
18
19
21
22
24
25
27
28
Table #2. Host/PCI Frequency Select (MHz)
FS1
FS0
HOST
0
0
66.66
0
1
60
1
0
75
1
1
50
Pin Assignment
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
15
20
19
17
18
25
24
23
22
21
26
27
28
HOST3
HOST4
GND
HOST5
HOST2
HOST1
X14O
GND
VDD
X14I
14.3(HS)
VDDHOST1-4
VDD
HOST5-7
EHOST6
Table #1. F1, F2 Frequency
Select (MHz)
SEL1
SEL0
0
0
0
1
1
0
1
1
Table #4. Power Down Control (IDD measured at 3.3V)
STOP# SLOW#
STATE
1
1
ON
1
0
SLOW
33 MHz
0
0
CLK OFF
0
1
PLL/OSC OFF
F1
F2
14.318
14.318
24.000
16.934
14.318
48.000
14.318
24.576
Low EMI for HOST & PCI
LE
Low EMI
0
OFF
1
ON
Key: I = Input, O = Output, P = Power supply connection, I/O = Input on power up, becomes an Output after 10ms.
Internal pull-ups are on pins 5, 16, 18, 19, 21, 22, 24, 25, 27, 28.
HS
0
1
2.5V
3.3V
Table #3. Host 5-7 Skew Control
VDD
HOST5-7
VDD
PCI(S/A)
PCI(FS0)
GND
PCIF(LE)
PCI(SEL1)
GND
VDD
F2(PS)
PCI(FS1)
STOP#
F1(SEL0)
HOST7
SLOW#
*PCI Function Select (PS) set at Power Up. PS=0, PCI=LOW; PS=1, PCI=ON when clock is switched to “CLK OFF” mode.
PCI (S/A=0)
33.33*
33.33*
33.33*
33.33*
PCI (S/A=1)
HOST/2
HOST/2
HOST/2
HOST/2
*2 MHz Accuracy
Name
VDD
X14I
X14O
GND
14.3(HS)
HOST 1, 2, 3, 4
VDD
HOST 5
EHOST 6
VDD
HOST7
SLOW#
PCI(FS0)
PCI(S/A)
PCI(SEL1)
PCIF(LE)
PCI(FS1)
F2(PS)
F1(SEL0)
STOP#
Type Description
P
Connect to +3.3V. Must be same voltage on all pins.
I
Crystal connection. Connect to a 14.31818 MHz crystal or input clock.
O
Crystal connection. Connect to a 14.31818 MHz crystal, or leave unconnected for clock.
P
Connect to Ground.
I/O 14.318 MHz output. Amplitude matches VDD. Skew input control for Host 5-7.
O
Host Output clocks 1, 2, 3 and 4. Amplitude matches VDD
P
Connect to VDD supply.
O
Host Output clock 5. Amplitude matches VDD .
O
Early Host Output clock 6. Amplitude matches VDD .
P
Connect to 2.5 V or 3.3 V. Host 5-7 skew adjusted with HS input. See Table #3 above.
O
Host Output clock 7. Amplitude matches VDD .
I
Controls clock frequency and power downs, as defined in Table #4 above.
I/O PCI Output clock, CPU Frequency Select input, as per Table #2 above. Amplitude = VDD.
I/O PCI Output clock, and Asynchronous PCI Select input, as per Table #2 above.
I/O PCI Output clock, and Frequency Select 1 input, as per Table #1 above.
I/O PCI Output clock that stays enabled when other PCI clocks are low. Low EMI enable input.
I/O PCI output and Frequency Select input. See Table #2 above.
I/O Fixed frequency output and PCI Function Select for "CLK OFF" mode.
I/O Fixed frequency output and frequency SEL0 input per Table #1 above.
I
Controls clock frequency and power downs, as defined in Table #4 above.
HOST1-4
HOST1-4
HOST5-7
HOST
ON
PCI
ON
ON
*
DESCRIPTION
All Clocks On.
Host Clock smooth frequency transition to and from 33.33 MHz.
Asynchronously clamp HOST5, 7 to GND. HOST1-4,6, PCIF, F1, F2, 14.3M, continue to run.
LOW All outputs asynchronously clamped low. PLLs and 14.3 MHz oscillators are off.
IDD typ.
50 mA
32 mA
44 mA
1 μA
LOW
LOW
HOST5-7
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