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參數(shù)資料
| 型號： | MK1491E-14R |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 75 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| 封裝： | SSOP-28 |
| 文件頁數(shù)： | 2/4頁 |
| 文件大?。?/td> | 70K |
| 代理商： | MK1491E-14R |
MK1491-14
OPTi ACPI Firestar Clock Source
MDS 1491-14 B
2
Revision 061801
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA 95126 (408)295-9800tel www.icst.com
Pin Descriptions
Table #2. Host/PCI Frequency Select (MHz)
Pin Assignment
1
8
9
2
3
4
5
6
7
10
11
12
13
14
16
15
20
17
18
19
25
24
23
22
21
26
27
28
HOST3
HOST2
HOST1
X14O
VDD
14.3(HS)
HOST4
VDDHOST1-4
X14I
GND
VDDHOST5-7
GND
EHOST6
HOST5
Table #1. F1, F2 Frequency
Select (MHz)
Table #4. Power Down Control (IDD measured at 3.3V)
SEL1
SEL0
F1
F2
0
14.318
0
1
14.318
48.000
1
0
24.000
14.318
1
16.934
24.576
Low EMI for HOST & PCI
LE
Low EMI
0
OFF
1
ON
Key: I = Input, O = Output, P = Power supply connection, I/O = Input on power up, becomes an Output after 10ms.
Internal pull-ups are on pins 5, 16, 18, 19, 21, 22, 24, 25, 27, 28.
HS
2.5V
0
3.3V
1
Table #3. Host 5-7 Skew Control
VDD
PCIF(LE)
GND
VDD
STOP#
PCI(S/A)
PCI(SEL1)
F1(SEL0)
F2(PS)
HOST7
PCI(FS0)
SLOW#
GND
PCI(FS1)
*PCI Function Select (PS) set at Power Up. PS=0, PCI=LOW; PS=1, PCI=ON when clock is switched to “CLK OFF” mode.
FS1
FS0
HOST
PCI (S/A=0)
PCI (S/A=1)
0
66.66
33.33*
HOST/2
0
1
60
33.33*
HOST/2
1
0
75
33.33*
HOST/2
1
50
33.33*
HOST/2
VDDHOST5-7
*2 MHz Accuracy
Pin #
Name
Type Description
1, 20, 26
VDD
P
Connect to +3.3V. Must be same voltage on all pins.
2
X14I
I
Crystal connection. Connect to a 14.31818 MHz crystal or input clock.
3
X14O
O
Crystal connection. Connect to a 14.31818 MHz crystal, or leave unconnected for clock.
4, 11, 17, 23
GND
P
Connect to Ground.
5
14.3(HS)
I/O 14.318 MHz output. Amplitude matches VDD. Skew input control for Host 5-7.
6, 7, 9, 10
HOST 1, 2, 3, 4
O
Host Output clocks 1, 2, 3 and 4. Amplitude matches VDD
8
VDD
P
Connect to VDD supply.
12
HOST 5
O
Host Output clock 5. Amplitude matches VDD
.
13
EHOST 6
O
Early Host Output clock 6. Amplitude matches VDD
.
14
VDD
P
Connect to 2.5 V or 3.3 V. Host 5-7 skew adjusted with HS input. See Table #3 above.
15
HOST7
O
Host Output clock 7. Amplitude matches VDD
.
16
SLOW#
I
Controls clock frequency and power downs, as defined in Table #4 above.
18
PCI(FS0)
I/O PCI Output clock, CPU Frequency Select input, as per Table #2 above. Amplitude = VDD.
19
PCI(S/A)
I/O PCI Output clock, and Asynchronous PCI Select input, as per Table #2 above.
21
PCI(SEL1)
I/O PCI Output clock, and Frequency Select 1 input, as per Table #1 above.
22
PCIF(LE)
I/O PCI Output clock that stays enabled when other PCI clocks are low. Low EMI enable input.
24
PCI(FS1)
I/O PCI output and Frequency Select input. See Table #2 above.
25
F2(PS)
I/O Fixed frequency output and PCI Function Select for "CLK OFF" mode.
27
F1(SEL0)
I/O Fixed frequency output and frequency SEL0 input per Table #1 above.
28
STOP#
I
Controls clock frequency and power downs, as defined in Table #4 above.
HOST1-4
HOST5-7
STOP# SLOW#
STATE
HOST
PCI
DESCRIPTION
IDD typ.
1
ON
All Clocks On.
50 mA
1
0
SLOW
33 MHz
ON
Host Clock smooth frequency transition to and from 33.33 MHz.
32 mA
0
CLK OFF
LOW
Asynchronously clamp HOST5, 7 to GND. HOST1-4,6, PCIF, F1, F2, 14.3M, continue to run.
44 mA
0
1
PLL/OSC OFF
LOW
LOW All outputs asynchronously clamped low. PLLs and 14.3 MHz oscillators are off.
1 A
*
HOST5-7
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