參數(shù)資料
型號: MK1491-09RTR
元件分類: 時鐘產(chǎn)生/分配
英文描述: 66 MHz, OTHER CLOCK GENERATOR, PDSO28
封裝: 0.209 INCH, SSOP-28
文件頁數(shù): 4/5頁
文件大?。?/td> 70K
代理商: MK1491-09RTR
MK1491-09
CS5535 Redcloud/Capistrano Clock Source
MDS 1491-09 A
4
Revision 110501
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA 95126 (408) 295-9800 www.icst.com
Power Down Control Table
Power-On Default Conditions
Input Pin#
Function
Default Condition
14
TS#
H
All outputs enabled.
27
Spread #
H
Spread disabled.
17
PD#
H
PCI clocks set to 33 MHz. Refer to Power Down Control Table above.
10
Sel66/33
H
PCI frequency = 66 MHz.
External Components
The MK1491-09 requires some inexpensive external components for proper operation. Decoupling capacitors of
0.1F should be connected on each VDD pin to ground, as close to the MK1491-09 as possible.
A series
termination resistor of 33
may be used for each clock output. See the discussion below for other external resistors
required for proper I/O operation.
The 14.318 MHz oscillator has internal caps that provide the proper load for a
parallel resonant crystal with CL=18 pF. For tuning with other values of CL, the formula 2*(CL-18) gives the value of
each capacitor that should be connected between X1 and ground and X2 and ground.
I/O Structure
The MK1491-09 provides more functionality in a 28 pin package
by using a unique I/O technique. The device checks the status
of all I/O pins during power-up. This status (pulled high or low)
then determines the frequency selections and power down
modes (see the tables on pages 2 and 4). Within 10ms after
power up, the inputs change to outputs and the clocks start up.
In the diagrams to the right, the 33
resistors are the normal
output termination resistors.
The 10k
resistor pulls low to
generate a logic zero when needed.
Weak internal pull-up
resistors are present on TS#, Spread #, PD#, and Sel66/33 to
pull the pin to high when left floating.
to load*
I/O
For select
= 0 (low)
10k
Don’t stuff for
“1” selection
33
*Note: Do not use a TTL load. This will
overcome the 10 k
pulldown and force the
input to a logic 1.
PD#
Functions
0
All clocks are stopped low.
1
All clocks are running.
相關(guān)PDF資料
PDF描述
MK1491-09R 66 MHz, OTHER CLOCK GENERATOR, PDSO28
MK1491-09RLF 66 MHz, OTHER CLOCK GENERATOR, PDSO28
MK1604-01STR 40.5 MHz, OTHER CLOCK GENERATOR, PDSO16
MK1631-01S 40.5 MHz, VIDEO CLOCK GENERATOR, PDSO16
MK1631-01STR 40.5 MHz, VIDEO CLOCK GENERATOR, PDSO16
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