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參數(shù)資料
| 型號： | MK1491-09FLNTR |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 66 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| 封裝： | 0.209 INCH, ROHS COMPLIANT, MO-150, SSOP-28 |
| 文件頁數(shù)： | 3/9頁 |
| 文件大?。?/td> | 165K |
| 代理商： | MK1491-09FLNTR |
AMD Geode GX2 Clock Source
MDS 1491-09 I
3
Revision 021506
Integrated Circuit Systems, Inc.
● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
MK1491-09
Pin Descriptions
KEY: I = Input, TI = Tri-level, O = Output, P = Power supply connection, (T)I/O = Input on power up,
becomes an Output after 10 ms, Weak internal pull-up resistors are present on TS#, Spread#, PD#, and
Sel66/33.
Pin
Number
Pin
Name
Pin
Type
Pin Description
1, 7, 11, 15, 21, 22
GND
P
Connect to Ground.
2
XI
I
Crystal connection. Connect to a 14.31818 MHz crystal or input clock.
3
XO
O
Crystal connection. Connect to a 14.31818 MHz crystal or leave
unconnected.
4, 8, 12, 19, 25, 28
VDD
P
Connect to 3.3 V.
5, 6, 9
LPC or
LCLK
O
33 MHz low skew clock outputs for LPC interface. These clocks are
synchronous outputs with low skew.
10
Sel66/33#
I
When high, the PCICLK runs at 66 MHz; when low, the PCICLK runs at
33 MHz. This pin has a weak internal pull-up resistor. This is an active
input, not a latched input.
13
48M
O
48 MHz clock output.
14
48M/TS#
I/O
48 MHz clock output. TS# is a latched input at power up and tristates all
outputs when low upon power up. When high upon power up, all
outputs are enabled. Power must be cycled for a change of state to be
detected. This pin has a weak internal pull-up resistor.
16
66M
O
66 MHz clock output.
17
PD#
I
Power-down input. This is an active input not latched input. When this
pin is set low, all clock outputs will be stopped, all PLL’s will be stopped,
and the oscillator will be powered off. Weak pull-up resistor (see Power
Down table).
18, 20, 23, 24
PCICLK
O
33 to 66 MHz PCI synchronous clock outputs with low skew.
26
RefCLK1
O
Buffered reference output of 14.31818 MHz.
27
RefCLK0/
Spread#
I/O
Buffered reference output of 14.31818 MHz. Spread# is a latched input
upon power up. Spread is applied to all clocks except REFCLK’s and
48 MHz. Power must be cycled for a change of state to be detected.
This pin has a weak internal pull-up resistor. See spread table.
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| MK1492-03RLF | 75 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
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| MK1492-03R | 75 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
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