參數(shù)資料
型號: MK1491-06STR
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘產(chǎn)生/分配
英文描述: 49.152 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28
封裝: 0.150 INCH, MO-153, SOIC-28
文件頁數(shù): 7/11頁
文件大?。?/td> 284K
代理商: MK1491-06STR
MK1491-06
AMD GEODE CLOCK SOURCE
CLOCK SYNTHESIZER
IDT / ICS AMD GEODE CLOCK SOURCE
5
MK1491-06
REV J 110204
External Components
The MK1491-06 requires some inexpensive external
components for proper operation. Decoupling capacitors of
0.1F should be connected on each VDD pin to ground, as
close to the MK1491-06 as possible. A series termination
resistor of 33
may be used for each clock output. See the
discussion below for other external resistors required for
proper I/O operation. The 14.3 MHz oscillator has internal
caps that provide the proper load for a parallel resonant
crystal with CL=18 pF. For tuning with other values of CL, the
formula 2*(CL-18) gives the value of each capacitor that
should be connected between X1 and ground and X2 and
ground.
I/O Structure
The MK1491-06 provides more functionality in a 28-pin
package by using a unique I/O technique. The device
checks the status of all I/O pins during power-up and at exit
from the Power Down state. This status (pulled high, low, or
mid-level) then determines the frequency selections and
power down modes (see the tables on pages 2 and 4).
Within 10ms after power up, the inputs change to outputs
and the clocks start up. In the diagrams to the right, the 33
resistors are the normal output termination resistors. The
10k
resistor pulls low to generate a logic zero. Weak
internal pull-up resistors are present on SEL24, EPCI#, FS,
LE#, PCISTP#, and SLOW#. These pins should be
connected directly to VDD or GND if not under active
control. Internal resistors on PEN, SEL AUDIO, and TS pull
to a mid-level (M).
*Note: Do not use a TTL load. This will overcome the 10 k
pull-down and force the input to a logic 1.
33
To load*
10 k
I/O
For select
= 0 (low)
Do not stuff for
“1” selection
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