參數(shù)資料
型號: MIC2564A-1BTS
廠商: MICREL INC
元件分類: 電源管理
英文描述: Dual Serial PCMCIA/CardBus Power Controller Preliminary Information
中文描述: 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO24
封裝: TSSOP-24
文件頁數(shù): 5/16頁
文件大?。?/td> 166K
代理商: MIC2564A-1BTS
MIC2564A
Micrel
September 1999
5
MIC2564A
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Serial Interface Timing Requirements
(See Figure 1),
Note 10
t
HD:DAT
t
SU:DAT
t
SU:SLA
t
SU:RST#
t
W
SDA Hold Time
75
ns
SDA Setup Time
data before clock
75
ns
Latch Setup Time
50
ns
Reset to Data Setup Time
RST# before data
50
ns
Minimum Pulse Width
clock (t
W:CLK
)
latch (t
W:SLA
)
reset (t
W:RST
)
data (t
W:DA
)
50
ns
100
ns
50
ns
50
ns
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Note 6.
Exceeding the absolute maximum rating may damage the device.
The device is not guaranteed to function outside its operating rating.
Devices are ESD sensitive. Handling precautions recommended.
Output enabled into short circuit.
Measurement is from the 50% point of the SLA rising edge.
Measurement is from the Hi-Z- or 0V-state command to the beginning of the slope. Measurement does not apply when device is in current
limit or thermal shutdown.
V
CC3
IN powers all internal logic, bias, and drive circuitry, and is required for operation.
V
PP
and V
CC5
IN are not required for operation.
V
IN must be either high impedance or greater than or approximately equal to the highest voltage V
CC
in the system. For example, if both
3.3V and 5V are connected to the MIC2564A, V
PP
IN must be either 5V, 12V, or high impedance.
Note 10.
Guaranteed by design not production tested.
Note 7.
Note 8.
Note 9.
Serial Control Timing Diagram
SDA
SLA
SCL
D8
D7
D6
D5
D4
D3
D2
D1
D0
t
SU:DAT
t
SU:SLA
t
HD:DAT
t
SU:RST#
RST#
t
W:DAT
t
W:CLK
t
W:SLA
Figure 1. Serial Control Timing Diagram
The MIC2564A uses a three-wire serial interface to control V
CC
and V
PP
outputs for both sections A and B. The three control
lines have thresholds compatible with both 3.3V and 5V logic families. Data (SDA) is clocked in on the rising clock edge. The
clock signal may be continuous or it may halt after all data is clocked in.
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