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參數(shù)資料
| 型號(hào)： | MIC2555-1YML TR |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 11/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX OTG USB BUS UNIV 24MLF |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 1/0 |
| 規(guī)程： | USB 2.0 |
| 電源電壓： | 3 V ~ 4.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤，24-MLF? |
| 供應(yīng)商設(shè)備封裝： | 24-MLF?（4x4） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 1113 (CN2011-ZH PDF) |
| 其它名稱： | 576-1088-6 |
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Micrel, Inc.
MIC2555
December 2006
19
M9999-121406
SCL, SDA
The serial clock (SCL) and serial data (SDA) signals
implement a two-wire I
2C serial bus for control of the
MIC2555. As with all I
2C busses the MIC2555 shares a
common external pull-up resistor on each line.
INT/
The interrupt (INT/) pin is asserted while an interrupt
condition exists. It is an open drain output so that it can
be wire-ORed with other interrupt signals, and requires
an external pull-up resistor to provide a logic output. The
pull-up voltage must not be greater than VBAT.
ADR0
Because some systems may have more than one
transceiver on the I
2C bus, OTG Transceivers have been
assigned four I
2C Address locations by convention.
MIC2555 address: 01011xxb (Bit order: A6
A0)
The ADR0 pin and MIC2555’s ‘dash number’ control the
‘xx’ of MIC2555’s address, where –0 or –1 specifies the
higher order bit’s value:
Part Number
Address Range
MIC2555BML-0
0x
MIC2555BML-1
1x
Where x = the state of ADR0
D+, D-
The data plus (D+) and data minus (D-) pins output the
USB data signals. When operating as a non-USB
transceiver, the role of D+, D- change:
UART mode:
D+ = RXD
D- = TXD
GPIO_1_TX, GPIO_0_RX, GPIO_2
GPIO_0, GPIO_1, and GPIO_2 are general purpose
I/Os that can be used as data ports or interrupt sources
for the system controller, display drivers or power
switches for actuators or annunciators.
These GPIO have open drain outputs capable of sinking
at least 10 mA, can be wire ORed together, and may be
pulled above the MIC2555’s operating supply voltage,
but not beyond the 6V absolute maximum allowed. As
logic inputs, the GPIO logic thresholds are standard
CMOS thresholds set by VDD_LGC voltage.
The GPIO Input Register is a read-only register and
shows real time status of the GPIOs, independent of
other I/O settings. The GPIO Output Register holds the
desired output value for each I/O. Each I/O can act as an
independent interrupt source and can be programmed
for triggering on T
F, F
T, or both transitions
simultaneously.
The GPIO pins serve double duty as active signal pins
when called into action by the appropriate control bit:
GPIO_0 = Secondary UART Receive input.
GPIO_1 = Secondary UART Transmit output.
GPIO_2 = External charge pump oscillator input.
Audio mode:
D+
D-
Stereo
D+
Mono
D-
Mic
These are generally agreed
upon, but are not
mandatory.
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