參數(shù)資料
型號: MIC2341-2YTQ
廠商: Micrel Inc
文件頁數(shù): 12/32頁
文件大?。?/td> 1277K
描述: IC HOT PLUG CTLR DUAL PCI 48TQFP
標(biāo)準(zhǔn)包裝: 250
類型: 熱交換控制器
應(yīng)用: 通用型,PCI Express?
內(nèi)部開關(guān):
電源電壓: 3.3V,12V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 48-TQFP
供應(yīng)商設(shè)備封裝: 48-TQFP(7x7)
包裝: 管件
產(chǎn)品目錄頁面: 1085 (CN2011-ZH PDF)
其它名稱: 576-2995
Micrel, Inc.
MIC2341/2341R
 
 
October 2007 
12
M9999-102507-A
 (408) 944-0800
 
AC Electrical Characteristics
(4)
 
12V
IN[A/B]
 = 12V, 3V
IN[A/B]
 = 3.3V, V
STBY[A/B]
 = 3.3V, T
A
 = 25癈, unless otherwise noted. Bold values specifications applies
over the full operating temperature range from 0癈 <
 T
A
 <
 +70癈. 
Symbol
Parameter
Condition
Min
Typ
Max
Units
t
OFF(12V)
 
12V Current Limit Response Time
(5)
 
(Figure 2)
MIC2341-2YTQ
CGATE[A/B] = 25pF
V
IN
 V
SENSE
 = 140mV
 
1
2.0
t
OFF(3V)
 
3.3V Current Limit Response
Time
(5)
 
(Figure 3)
MIC2341-2YTQ
CGATE[A/B] = 25pF
V
IN
 V
SENSE
 = 140mV
 
1
2.0
t
SC(TRAN)
 
VAUX[A/B] Current Limit
Response Time (Figure 5)
VAUX[A/B] = 0V, VSTBY[A/B] = +3.3V
 
2.5
5
t
PROP(12VFAULT)
 
Delay from 12VOUT[A/B]
Overcurrent Limit to
/FAULT_MAIN[A/B] = LOW
(5)
 
MIC2341-2YTQ
CFILTER[A/B] = OPEN
V
IN
 V
SENSE
 = 140mV
 
 
1
t
PROP(3VFAULT)
 
Delay from 3VOUTA/B]
Overcurrent Limit to
/FAULT_MAIN[A/B] = LOW
(5)
 
 MIC2341-2YTQ
CFILTER[A/B] = OPEN
V
IN
 V
SENSE
 = 140mV
 
 
2
t
PROP(VAUXFAULT)
     Delay on VAUX[A/B] Overcurrent
from CFILTER time out (V
CFILTER
= V
FILTER
) to
 /FAULT_AUX[A/B] = LOW
(5)
 
MIC2341-2YTQ
limit to /FAULT_AUX[A/B] output
CFILTER[A/B] = 50pF
V
AUX
 Output Grounded
 
10
 
t
LPW
 
ON[A/B], AUXEN[A/B] Low Pulse
Width to Reset Output Upon Fault
Removal
(5)
 
ON[A/B], AUXEN[A/B]
   = HIGH-to-LOW-HIGH
200
 
 
ns
t
INTCLK
 
Digital Filter (Internal Clock)
Period
 
5
 
15
t
POR
 
MIC2341 Power-On Reset Time
after VSTBY[A/B] becomes valid
(5)
 
 
80
 
255
t
/CRSW[A/B]
 
/CRSW[A/B] Debounce Delay
Time
 
5.10
 
15.85
ms
t
/PWRGD
 
/PWRGD[A/B] De-assertion Delay
Time
ON[A/B] or AUXEN[A/B] High-to-Low
Transition
640
 
2040
t
/DLY_PWRGD
 
/DLY_PWRGD[A/B] Assertion
Delay after /PWRGD[A/B]
Assertion
ON[A/B], AUXEN[A/B] = HIGH,
12VOUT[A/B], 3VOUT[A/B], VAUX[A/B] =
VALID;
80
 
 
241
ms
t
DFLT
 
Internal Primary OC Detector
Response Time
(MIC2341 and MIC2341R)
CFILTER[A/B] = GND
20.5
41
 
63.5
ms
t
AUTO RETRY
 
Auto Retry Period
(MIC2341R only)
 
410
 
1236
ms
Notes:
1.    Exceeding measurements given within the Absolute Maximum Ratings section may damage the device.
2.    The device is not guaranteed to function outside of the measurements given in the Operating Ratings section.
3.    These devices are ESD sensitive. Employ proper handling precautions. The HBM is 1.5k& in series with 100pF.
4.    Specifications apply to packaged product only.
5.    Parameters guaranteed by design, not subject to test.
 
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