4-198
MH89790B
Preliminary Information
Table 14. Master Status Word 1 (MSW1): Data Format for CSTo Channel 18
Table 15. Phase Status Word (PSW): Data Format for CSTo Channel 19
Table 16. CRC Error Count: Data Format for CSTo Channel 20
Table 17. Master Status Word 2 (MSW2): Data Format for CSTo Channel 21
BIT
NAME
DESCRIPTION
7
TFSYN
Frame Sync:
This bit goes to ‘1‘ to indicate a loss of frame alignment synchronization by the
MH89790B. It goes to ‘0‘ when frame synchronization is detected.
6
MFSYN
Multiframe Sync:
This bit goes to ‘1‘ to indicate a loss of multiframe synchronization by the
MH89790B. It goes to ‘0‘ when multiframe synchronization is detected.
5
ERR
Frame Alignment Error:
This bit changes state when 16 or more errors have been detected in
the frame alignment signal. It will not change state more than once every 128 ms.
4
SLIP
Control Slip:
This bit changes state when a slip occurs between the received CEPT 2048 kbit/s
link and the 2048 kbit/s ST-BUS.
3
RXAIS
Receive Alarm Indication Signal:
This bit goes to ‘1‘ to signal that an all-ones alarm signal has
been detected on the received CEPT 2048 kbit/s link. It goes to ’0’ when the all-ones alarm
signal is removed.
2
RXTS16AIS
Receive Timeslot 16 Alarm Indication Signal:
This bit goes to ‘1‘ to signal that an all-ones
alarm signal has been detected on channel 16 of the received CEPT 2048 kbit/s link. It goes to
‘0‘ when the all-ones alarm signal is removed.
1
XSt
External Status:
This bit contains the data sampled once per frame at the XSt pin.
0
N/A
(Unused).
BIT
NAME
DESCRIPTION
7 - 3
TxTSC
Transmit Timeslot Count:
The value of these five bits indicate the timeslot count between the
ST-BUS frame pulse and the rising edge of E8Ko.
2 - 0
TxBTC
Transmit Bit Count:
The value of these three bits indicate the bit position within the timeslot
count reported in TxTSC above.
BIT
NAME
DESCRIPTION
7 - 0
CERC
CRC Error Counter:
This byte is the CRC error counter. The counter will wrap around once it
reaches FF count. If maintenance option is activated, the counter will reset once per second.
BIT
NAME
DESCRIPTION
7
Si2
The received Si bit in frame 15 is reported in this bit. Si2 will be updated after each
RXMF pulse (pin 23).
6
Si1
The received Si bit in frame 13 is reported in this bit. Si1 will be updated after each
RXMF pulse (pin 23).
5-4
NA
Unused.
3
CRCTimer
CRC Timer:
Transition from 1 to 0 indicates the start of one second interval in which CRC errors
are accumulated. This bit stay high for 8 ms.
2
CRCRef
CRC Reframe:
A ’1’ indicates that the receive CRC multiframe synchronization could not be
found within the time out period of 8 ms after detecting frame synchronization. This bit will go low
if CRCSync goes low or if Maintenance is not activated.
1
CRCSync
CRC Sync:
A ’0’ indicates that CRC multiframing has been detected.
0
FrmPhase
Frame Count:
This is the ninth and most significant bit of the Phase Status Word (see Table 15).
If the phase status word is incrementing, this bit will toggle when the phase reading exceeds
ST-BUS channel 31, bit 7. If the phase word is decrementing, then this bit will toggle when the
reading goes below ST-BUS channel 0, bit 0.