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參數(shù)資料
| 型號(hào)： | MH89770S |
| 廠商： | Mitel Networks Corporation |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁(yè)數(shù)： | 17/36頁(yè) |
| 文件大?。?/td> | 836K |
| 代理商： | MH89770S |
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4-141
Preliminary Information
MH89770
Figure 9 - Reframe Time
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Reframe Time (ms)
Percentage Reframe Time Probability Versus Reframe Time
With Pseudo Random Data
D4
ESF
The out of sync threshold can be changed from 2 out
of 4 errors in F
T
(or FPS) to 4 out of 12 errors in F
T
(or FPS). The average reframe time is 24 ms for ESF
mode, and 12ms for D3/D4 modes.
Figure 9 is a bar graph which shows the probability
of achieving frame synchronization at a specific time.
The chart shows the results for ESF mode with CRC
check, and D3/D4 modes of operation. The average
reframe time with random data is 24 ms for ESF, and
13 ms for D3/D4 modes. The probability of a
reframe time of 35 ms or less is 88% for ESF
mode, and 97% for D3/D4 modes. In ESF mode it is
recommended that the CRC check be enabled
unless the line has a high error rate. With the CRC
check disabled the average reframe time is greater
because the framer must also check for mimics.
Applications
1. Typical T1 Application
Figure 10 shows the external components that are
required in a typical T1 application using the
MH89770. The MT8980 is used to control and
monitor the device as well as
switch data to DSTi and
DSTo (refer to Application Note MSAN-123 for more
information on the operation of the MT8980). The
MT8952, HDLC protocol controller, is shown in this
application to illustrate how the data on the FDL
could be used. The digital phase-locked loop, the
MT8941, provides all the clocks necessary to make
a functional interface. The 1.544 MHz clock
extracted by the MH89770 is used to clock in data at
RxT and RxR. It is also internally divided by 193 to
obtain an 8 kHz clock which is output at E8Ko. The
MT8941 uses this 8 kHz signal to provide a phase
locked 2.048 MHz clock for the ST-BUS interface
and a 1.544 MHz clock for the DS1 transmit side.
Note: the configurations shown in Figures 10 and 12
using the MT8941 may not meet specific jitter
performance requirements. A more sophisticated
PLL may be required for applications designed to
meet specific standards. Please refer to the MT8941
data sheet for further details on its jitter performance.
The split phase unipolar signals output by the
MT8977 at TxA and TxB are used by the line driver
circuit to generate a bipolar AMI signal. The line
driver is transformer coupled to an equalization
circuit and the DS1 line. Equalization of the
transmitted signal is required to meet AT & T
specifications
for
crossconnect
equip-ment (see AT&T Technical Advisory #34).
Specifica-tions for the input and output transformers
are shown in Figure 11. On the receive side the
bipolar line signal is converted into a unipolar format
by the line receiver circuit. The resulting split phase
signals are input at the RxA and RxB pins on the
compatible
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MH89790B | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MH89790BN | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MH89790BS | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MH89791 | CEPT PCM 30 Transmit Equalizer Advance Information |
| MH89792-1 | E1 Transceiver Preliminary Information |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MH89790B | 制造商:MITEL 功能描述: 制造商:ZARLNK 功能描述: |
| MH89790BN | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:ST-BUS⑩ FAMILY CEPT PCM 30/CRC-4 Framer & Interface Preliminary Information |
| MH89790BS | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:ST-BUS⑩ FAMILY CEPT PCM 30/CRC-4 Framer & Interface Preliminary Information |
| MH89791 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CEPT PCM 30 Transmit Equalizer Advance Information |
| MH89792 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:E1 Transceiver Preliminary Information |
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