2-280
MH89625C
Preliminary Information
Hybrid
The 2-4 Wire hybrid circuit separate the 2-wire
balanced full duplex signal at Tip and Ring of the
telephone line into 4-wire receive and transmit
ground referenced analog signals internal to the
SLIC. These analog signals are internally connected
to the MT8967 Filter/Codec which translates the
analog signals to digital PCM. The hybrid also
includes cancellation circuitry which prevents the
input PCM signal at DSTi from appearing at DSTo.
The degree to which the Hybrid minimizes the
contribution of the input signal at DSTi from
appearing at the DSTo output is specified as
transhybrid loss. See the Network Balance section
for maximizing transhybrid loss.
Return Loss
To maximize return loss, the impedance at Tip-Ring
should match the SLIC’s input impedance (Z
in
).
Network Balance
Transhybrid loss is maximized when the line
termination impedance and the SLIC’s network
balance are matched. The MH89625C’s network
balance impedance is automatically internally set to
match the SLIC’s input impedance (Z
in
). Therefore,
the SLIC’s transhybrid loss is maximized when the
line termination impedance and the SLIC’s input
impedance (Z
in
) are matched.
Tip-Ring Drive Circuit
The PCM input ground referenced signal at DSTi is
converted to a balanced output signal at Tip and
Ring. The Tip-Ring Drive Circuit is optimized for
good 2-wire longitudinal balance.
Tip-Ring Receive Gain
The differential audio signal at Tip and Ring is
converted to a ground referenced PCM signal at the
DSTo output.
Transmit Gain
Transmit Gain (Tip-Ring to DSTo) and Receive Gain
(DSTi to Tip-Ring) are programmed in 1dB steps by
writing to the Codec’s Control Register A via the
CSTi serial data stream. In addition, a Receive Gain
adjustment is provided which when activated
provides an additional -0.5dB gain. Refer to control
of SLIC gain.
Short Circuit Protection
The MH89625C is protected from long term (infinite)
short circuit conditions occurring between Tip and
Ring, Tip and AGND, and Ring and AGND.
Protection Circuit Design
The high voltage protection circuit is the MH80625C
which can be used in conjunction with the
MH89625C to meet the CCITT K.20 specification.
See Figures 3 and 4. The protection circuit consists
of 1 MOSFET Transistor (BUZ 22) per 16 lines and 4
voltage clamping diodes (IN4004) per line circuit.
This protection circuit will dissipate the lightning and
AC power energy to protect the line circuit. The
Energy Dump Ground (EDG) is tied to the chassis of
the system ground. The PCB E.D.G. track to the
MOSFET must be run separately. The width of the
ground track should be greater than 0.050 thou and
the resistance should be kept as low as possible,
less than 1 ohm. The MOSFET requires a heat sink
of 9°C/W to dissipate the heat generated by the
overvoltages
Mechanical Data
See Figure 6.