參數(shù)資料
型號(hào): MH16M40AJD-6
廠商: Mitsubishi Electric Corporation
英文描述: FAST PAGE MODE ( 16,777,216-WORD BY 40-BIT ) DYNAMIC RAM
中文描述: 快速頁(yè)面模式(16,777,216字40位)動(dòng)態(tài)隨機(jī)存儲(chǔ)器
文件頁(yè)數(shù): 6/17頁(yè)
文件大?。?/td> 189K
代理商: MH16M40AJD-6
MITSUBISHI
ELECTRIC
( / 17 )
6
FAST PAGE MODE ( 16,777,216-WORD BY 40-BIT ) DYNAMIC RAM
MH16M40AJD -6
MITSUBISHI LSIs
31/ Jan./1997
MIT - DS - 0069 -1.1
Proto-2
Preliminary Spec.
Some of contents are subject to change without notice.
Read-Write and Read-Modify-Write Cycles
Note 21: t
RWC
is specified as t
RWC(min)
=t
RAC(max)
+t
ODD(min)
+t
RWL(min)
+t
RP(min)
+4t
T.
22: t
WCS
, t
CWD
,t
RWD
and t
AWD
and,t
CPWD
are specified as reference points only. If t
WCS
t
WCS(min)
the cycle is an early write cycle and the
DQ pins will remain high impedance throughout the entire cycle. If t
CWD
t
CWD(min),
t
RWD
t
RWD (min),
t
AWD
t
AWD(min)
and t
CPWD
t
CPWD(min)
(for fast page mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address.
If neither of the above condition (delayed write) of the DQ (at access time and until CAS or OE goes back to V
IH
) is indeterminate.
ü
Fast-Page Mode Cycle (Read, Early Write, Read -Write, Read-Modify-Write Cycle)
(Note 23)
Limits
Parameter
Read write/read modify write cycle time
RAS low pulse width
CAS low pulse width
CAS hold time after RAS low
RAS hold time after CAS low
Symbol
t
RWC
Unit
Min
150
Max
ns
ns
ns
ns
ns
ns
ns
ns
t
RAS
t
CAS
t
CSH
t
RSH
t
RCS
t
CWD
t
RWD
Read setup time before CAS low
Delay time, CAS low to W low
Delay time, RAS low to W low
(Note21)
(Note22)
ns
ns
ns
50
95
50
95
0
30
75
15
15
10
45
t
AWD
t
CWL
t
RWL
t
WP
Delay time, address to W low
CAS hold time after W low
RAS hold time after W low
Write pulse width
Data setup time ü
Data hold time a
OE hold time after W low
t
DS
t
DH
t
OEH
0
15
10
ns
ns
ns
ns
(Note22)
(Note22)
10000
10000
Note 23: All previously specified timing requirements and switching characteristics are applicable to their respective fast page mode cycle.
24: t
RAS(min)
is specified as two cycles of CAS input are performed.
25: t
CP(max)
is specified as a reference point only. If tCP tCP(max),access time is controlled exclusively by tCAC.
Limits
-6
Parameter
Fast page mode read/write cycle time
RAS iow pulse width for read write cycle
CAS high pulse width
RAS hold time after CAS precharge
Symbol
t
PC
t
PRWC
t
RAS
Unit
Min
Max
ns
ns
ns
ns
ns
ns
t
CP
t
CPRH
t
CPWD
(Note24)
(Note25)
Delay time, CAS precharge to W iow
(Note22)
Fast page mode read write/read modify write cycle time
35
35
40
75
100
10
15
102400
CAS before RAS Refresh Cycle
(Note 26)
Limits
Parameter
CAS setup time before RAS low
CAS hold time after RAS low
Symbol
t
CSR
Unit
Min
10
Max
ns
ns
ns
ns
t
CHR
t
RSR
t
RHR
Read setup time before RAS low
Read hold time after RAS low
10
10
10
Note 26: Eight or more CAS before RAS cycles instead of eight RAS cycles are necessary for proper operation of CAS before RAS refresh
mode.
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-6
I
I
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