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參數(shù)資料
| 型號(hào)： | MG-5100SA |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO14 |
| 封裝： | ROHS COMPLIANT, SO-14 |
| 文件頁(yè)數(shù)： | 1/1頁(yè) |
| 文件大小： | 126K |
| 代理商： | MG-5100SA |
52
MULTI-OUTPUT CRYSTAL OSCILLATOR
MG - 5100SA series
Product number (Please contact us)
Q33M21SA1xxxxx00
Frequency range
: 76.9 kHz to 100 MHz
Operating voltage
: 3.3 V or 5.0 V
Built-in crystal
: AT crystal unit
Thickness
: 3.2 mm Typ.
Lead(Pb)-free
: Compl
ies with EU RoHS directive
Available output in 8 frequencies by selecting pin
for CPU CLK.
■ Specifications (characteristics)
Specifications
Item
Symbol
VDD=5.0V
VDD=3.3V
Remarks
Output frequency range
f0
76.9 kHz to 100 MHz
76.9 kHz to 80 MHz
Please contact us for inquiries about the available frequency.
Max. supply voltage
VDD-GND
-0.3 V to +7.0 V
Power source
voltage
Operating voltage
VDD
5.0 V ±0.5 V
3.3 V ±0.3 V
Storage temperature
TSTG
-55
°C to +100 °C
Stored as bare product after unpacking
Temperature
range
Operating temperature
TOPR
-20
°C to +70 °C
Frequency stability
f/f0
±100 × 10-6
Current consumption
IOP
100 mA Max.
65 mA Max.
No load, Max. frequency
Duty
tw/t
40 % to 60 %
50 % VDD, CL=15 pF
High output voltage
VOH
VDD-0.4 V Min.
IOH=-4 mA
Low output voltage
VOL
0.4 V Max.
IOL=4 mA
Output condition
CL
15 pF Max.
Max. frequency and Max. operating voltage
VIH
80 % VDD Min.
Output enable /
disenable input voltage
VIL
20 % VDD Max.
Output rise time
tR
5 ns Max.
20 %
→80 % VDD
Output fall time
tF
4 ns Max.
80 %
→20 % VDD
450 ps Max.
Cycle to Cycle jitter
Jitter
tj
500 ps Max.
Peak to Peak jitter
Skew
tskw
500 ps Max
Please contact us for inquiries about details.
Oscillation start up time
tOSC
70 ms Max.
Time at minimum operating voltage to be 0s.
Aging
fa
±5 × 10-6 / year Max.
Ta=+25
°C,VDD=5.0 V/ 3.3 V, First year
■ Block diagram
■ External dimensions
(Unit:mm)
■ Recommended soldering pattern
(Unit:mm)
Crystal oscillator
#14
# 1
# 7
# 8
0.7
1.27
7.62
2.0
5.4
2.
0
OSC.
PLL 1
PLL 2
PLL 3
ROM AND LOGIC
OUTPUT
MULTIPLEXER
AND
DIVIDERS
TIN
S2
S1
S0
OE
XBUF
CPUCLK
CLKA
CLKB
CLKC
CLKD
Pin terminal
XBUF
Output pin of internal X’tal
CPUCLK
Output pin
CLKA
Output pin
CLKB
Output pin
CLKC
Output pin
CLKD
Output pin
S0
CPUCLK Output frequency select pin 0
S1
CPUCLK Output frequency select pin 1
S2
CPUCLK Output frequency select pin 2
TIN
Test pin.Do not connect them to any terminals.
OE
Output control ("H"? Output ,"L"? weak pull - down)
Metal may be exposed on the top or bottom of this product.
This won't affect any quality, reliability or electrical spec.
0.6
0.15
0
° - 10°
10.1
± 0.2
5.
0
7.
4
±0.
2
#14
#8
#7
#1
1.27
1.2
0.05
Min.
3.
2
±0.
1
0.35
M5100 AB
E 935 6A
No.
Pin terminal
No.
Pin terminal
1
S1
14
VDD1
2
S0
13
VDD2
3
CLKA
12
S2
4
CLKB
11
OE
5
CPUCLK
10
CLKC
6
CLKD
9
GND
7
XBUF
8
TIN
Actual size
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