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參數(shù)資料
| 型號： | MCZ33904B5EKR2 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 68/106頁 |
| 文件大?。?/td> | 0K |
| 描述： | SENSOR ABS PRESS 56.6 PSI MAX |
| 標準包裝： | 1,000 |
| 應用： | 系統(tǒng)基礎芯片 |
| 接口： | CAN，LIN |
| 電源電壓： | 5.5 V ~ 27 V |
| 封裝/外殼： | 32-BSOP（0.295"，7.50mm 寬）裸露焊盤 |
| 供應商設備封裝： | 32-SOICW 裸露焊盤 |
| 包裝： | 帶卷 (TR) |
| 安裝類型： | 表面貼裝 |
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Analog Integrated Circuit Device Data
64
Freescale Semiconductor
33903/4/5
SERIAL PERIPHERAL INTERFACE
DETAIL OPERATION
DETAIL OPERATION
SPI Operation Deviation (does not apply to “C” version)
In some cases, the SPI write command is not properly
interpreted by the device. This results in either a “non
received SPI command” or a “corrupted SPI command”.
Important: Due to this, the tLEAD and tCSLOW parameters
must be carefully acknowledged.
Only SPI write commands (starting with bits 15,14 = 01)
are affected. The SPI read commands (starting with bits
15,14 = 00 or 11) are not affected.
The occurrence of this issue is extremely low and is
caused by the synchronization between internal and external
signals. In order to guarantee proper operation, the following
steps must be taken.
1. Ensure the duration of the Chip Select Low (tCSLOW)
state is >5.5
s.
Note: In data sheet revisions prior to 7.0, this parameter is
not specified and is indirectly defined by the sum of 3
parameters, tLEAD + 16 x tPCLK + tLAG (sum = 4.06 s).
2. Ensure SPI timing parameter tLEAD is a min. of
550 ns.
Note: In data sheet revisions prior to 7.0, the tLEAD
parameter is a min of 30 ns.
3. Make sure to include a SPI read command after a
SPI write command.
In case a series of SPI write commands is used, only one
additional SPI read is necessary. The recommended SPI
read command is “device ID read: 0x2580” so device
operation is not affected (ex: clear flag). Other SPI read
commands may also be used.
When the previous steps are implemented, the device will
operate as follows:
For a given SPI write command (named SPI write ‘n’):
In case the SPI write command ‘n’ is not accepted, the
following SPI command (named SPI ‘n+1’) will finish the
write process of the SPI write ‘n’, thanks to step 2
(tLAG > 550 ns) and step 3 (which is the additional SPI
command ‘n+1’).
By applying steps 1, 2, and 3, no SPI command is ignored.
Worst case, the SPI write ‘n’ is executed at the time the
SPI ‘n+1’ is sent. This will lead to a delay in device
operation (delay between SPI command ‘n’ and ‘n+1’).
Note: Occurrence of an incorrect command is reduced,
thanks to step 1 (extension of tCSLOW duration to >5.5 s).
Sequence examples:
Example 1:
0x60C0 (CAN interface control) – in case this command is
missed, next write command will complete it
0x66C0 (LIN interface control) – in case this command is
missed, next read command will complete it
0x2580 (read device ID) – Additional command to
complete previous LIN command, in case it was missed
Example 2:
0x60C0 (CAN interface control) - in case this command is
missed, next write command will complete it
0x66C0 (LIN interface control) - in case this command is
missed, next read command will complete it
0x2100 (read CAN register content) – this command will
complete previous one, in case it was missed
0x2700 (read LIN register content)
BITS 15, 14, AND 8 FUNCTIONS
Table 12 summarizes the various SPI operation, depending upon bit 15, 14, and 8.
Table 12. SPI Operations (bits 8, 14, & 15)
Control Bits MOSI[15-14], C1-C0
Type of Command
Parity/Next
MOSI[8] P/N
Note for Bit 8 P/N
00
Read back of register
content and block (CAN,
I/O, INT, LINs) real time
state. See Table 39.
1
Bit 8 must be set to 1, independently of the parity function
selected or not selected.
01
Write to register
address, to control the
device operation
0
If bit 8 is set to “0”: means parity not selected OR
parity is selected AND parity = 0
1
if bit 8 is set to “1”: means parity is selected AND parity = 1
10
Reserved
11
Read of device flags
form a register address
1
Bit 8 must be set to 1, independently of the parity function
selected or not selected.
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