DETAIL OF CONTROL BITS AND REGISTER MAPPING" />
參數(shù)資料
型號(hào)： MCZ33903BD5EK
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 75/106頁(yè)
文件大?。?/td> 0K
描述： IC SBC CAN HS 5.0V 32SOIC
標(biāo)準(zhǔn)包裝： 42
應(yīng)用： 系統(tǒng)基礎(chǔ)芯片
接口： CAN，LIN
電源電壓： 5.5 V ~ 28 V
封裝/外殼： 32-SSOP（0.295"，7.50mm 寬）裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 32-SOICW 裸露焊盤(pán)
包裝： 管件
安裝類型： 表面貼裝
Analog Integrated Circuit Device Data
70
Freescale Semiconductor
33903/4/5
SERIAL PERIPHERAL INTERFACE
DETAIL OF CONTROL BITS AND REGISTER MAPPING
Table 18. Initialization Watchdog Registers, INIT watchdog (note: register can be written only in INIT mode)
MOSI First Byte [15-8]
[b_15 b_14] 0_0110 [P/N]
MOSI Second Byte, bits 7-0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
01 00 _ 110 P
WD2INT
MCU_OC
OC-TIM
WD Safe
WD_spi[1]
WD_spi[0]
WD N/Win
Crank
Default state
0
1
0
1
0
Condition for default
POR
Bit
Description
b7
WD2INT - Select the maximum time delay between INT occurrence and INT source read SPI command
0
Function disable. No constraint between INT occurrence and INT source read.
1
INT source read must occur before the remaining of the current watchdog period plus 2 complete watchdog periods.
b6, b5
MCU_OC, OC-TIM - In LP VDD ON, select watchdog refresh and VDD current monitoring functionality. VDD_OC_LP threshold is defined in device
electrical parameters (approx 1.5 mA)
In LP mode, when watchdog is not selected
no watchdog
+ 00
In LP VDD ON mode, VDD overcurrent has no effect
no watchdog
+ 01
In LP VDD ON mode, VDD overcurrent has no effect
no watchdog
+ 10
In LP VDD ON mode, VDD current > VDD_OC_LP threshold for a time > 100 s (typically) is a wake-up event
no watchdog
+ 11
In LP VDD ON mode, VDD current > VDD_OC_LP threshold for a time > I_mcu_OC is a wake-up event. I_mcu_OC time is selected in Timer register
(selection range from 3.0 to 32 ms)
In LP mode when watchdog is selected
watchdog +
00
In LP VDD ON mode, VDD current > VDD_OC_LP threshold has no effect. watchdog refresh must occur by SPI command.
watchdog +
01
In LP VDD ON mode, VDD current > VDD_OC_LP threshold has no effect. watchdog refresh must occur by SPI command.
watchdog +
10
In LP VDD ON mode, VDD overcurrent for a time > 100 s (typically) is a wake-up event.
watchdog +
11
In LP VDD ON mode, VDD current > VDD_OC_LP threshold for a time < I_mcu_OC is a watchdog refresh condition. VDD current > VDD_OC_LP
threshold for a time > I_mcu_OC is a wake-up event. I_mcu_OC time is selected in Timer register (selection range from 3.0 to 32 ms)
b4
WD Safe - Select the activation of the SAFE pin low, at first or second consecutive RESET pulse
0
SAFE pin is set low at the time of the RST pin low activation
1
SAFE pin is set low at the second consecutive time RST pulse
b3, b2
WD_spi[1] WD_spi[0] - Select the Watchdog (watchdog) Operation
00
Simple Watchdog selection: watchdog refresh done by a 8 bits or 16 bits SPI
01
Enhanced 1: Refresh is done using the Random Code, and by a single 16 bits.
10
Enhanced 2: Refresh is done using the Random Code, and by two 16 bits command.
11
Enhanced 4: Refresh is done using the Random Code, and by four 16 bits command.
b1
WD N/Win - Select the Watchdog (watchdog) Window or Timeout operation
0
Watchdog operation is TIMEOUT, watchdog refresh can occur anytime in the period
1
Watchdog operation is WINDOW, watchdog refresh must occur in the open window (second half of period)
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