參數(shù)資料
型號: MCP9803-M/MSG
元件分類: 溫度/濕度傳感器
英文描述: DIGITAL TEMP SENSOR-SERIAL, 12BIT(s), 3Cel, SQUARE, SURFACE MOUNT
封裝: LEAD FREE, PLASTIC, MO-187, MSOP-8
文件頁數(shù): 8/30頁
文件大?。?/td> 478K
代理商: MCP9803-M/MSG
MCP9800/1/2/3
DS21909B-page 16
2004 Microchip Technology Inc.
5.0
SERIAL COMMUNICATION
5.1
2-Wire I2C/SMBus Compatible
Interface
The MCP9800/1/2/3 serial clock input (SCLK) and the
bidirectional serial data line (SDA) form a 2-Wire
bidirectional serial port for communication.
The following bus protocol has been defined:
TABLE 5-1:
MCP980X SERIAL BUS
CONVENTIONS
5.1.1
DATA TRANSFER
Data transfers are initiated by a start condition
(START), followed by a 7-bit device address and a 1-bit
read/write. Acknowledge (ACK) from slave confirms
the reception of each byte. Each access must be
terminated by a stop condition (STOP).
Data transfer may be initiated when the bus is in IDLE.
5.1.2
MASTER/SLAVE
The bus is controlled by a master device (typically a
microcontroller) that controls the bus access and gener-
ates the start and stop conditions. The MCP9800/1/2/3
is a slave device and does not control other devices in
the bus. Both master and slave devices can operate as
either transmitter or receiver. However, the master
device determines which mode is activated.
5.1.3
START/STOP CONDITION
A high-to-low transition of the SDA line (while SCLK is
high) is the start condition. All data transfers must be
preceded by a start condition from the master. If a start
condition is generated during data transfer, the
MCP9800/1/2/3 resets and accepts the new start
condition.
A low-to-high transition of the SDA line (while SCLK is
high) is the stop condition. All data transfers must be
ended by a stop condition from the master. If a stop
condition is introduced during data transmission, the
MCP9800/1/2/3 releases the bus.
5.1.4
ADDRESS BYTE
Following the start condition, the host must transmit the
address byte to the MCP9800/1/2/3. The 7-bit address
for
the
MCP9800/02A0
and
MCP9800/02A5
is
<1001000> and <1001101> in binary, respectively.
The
address
for
the
MCP9802/03
is
<1001,A2,A1,A0> in binary, where the A0, A1 and A2
bits are set externally by connecting the corresponding
pins to VDD <1> or GND <0>. The 7-bit address trans-
mitted in the serial bit stream must match the selected
address for the MCP9800/1/2/3 to respond with an
ACK.
Bit 8 in the address byte is a read/write bit. Setting this
bit to ‘1’ commands a read operation, while ‘0’
commands a write operation.
FIGURE 5-1:
Device Addressing.
Term
Description
Transmitter Device sending data to the bus
Receiver
Device receiving data from the bus
Master
The device that controls the serial bus,
typically a microcontroller
Slave
The device addressed by the master,
such as the MCP9800/1/2/3
START
A unique signal from master to initiate
serial interface with a slave
STOP
A unique signal from the master to
terminate serial interface from a slave
Read/Write
A read or write to the MCP9800/1/2/3
registers
ACK
A receiver Acknowledges (ACK) the
reception of each byte by polling the
bus
NAK
A receiver Not-Acknowledges (NAK) or
releases the bus to show End-of-Data
(EOD)
Busy
Communication is not possible
because the bus is in use
Not Busy
The bus is in the idle state, both SDA
and SCLK remain high
Data Valid
SDA must remain stable before SCLK
becomes high in order for a data bit to
be considered valid. During normal
data transfers, SDA only changes state
while SCLK is low
1
2
34
567
8
9
SCLK
SDA
10
0
1 A2A1A0
Start
Address Byte
Slave
Address
R/W
MCP9800/1/2/3 Response
Code
Address
A
C
K
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