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參數(shù)資料
| 型號(hào)： | MCP795W22-I/ST |
| 廠商： | Microchip Technology |
| 文件頁(yè)數(shù)： | 12/13頁(yè) |
| 文件大小： | 0K |
| 描述： | IC RTCC 64B SRAM WD/DET 14TSSOP |
| 標(biāo)準(zhǔn)包裝： | 96 |
| 類型： | 時(shí)鐘/日歷 |
| 特點(diǎn)： | 警報(bào)，EEPROM，閏年，方波輸出，SRAM，唯一 ID，看門狗定時(shí)器 |
| 存儲(chǔ)容量： | 64B |
| 時(shí)間格式： | HH:MM:SS:hh（12/24 小時(shí)） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | SPI |
| 電源電壓： | 1.8 V ~ 5.5 V |
| 電壓 - 電源，電池： | 1.3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-TSSOP |
| 包裝： | 管件 |
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2011-2012 Microchip Technology Inc.
Preliminary
DS22280C-page 7
MCP795W1X/MCP795W2X
2.11
RTCC Memory Map
The RTCC registers are contained in addresses 0x00h-
0x1fh. 64 bytes of user-accessable SRAM are located
in the address range 0x20-0x5f. The SRAM memory is
a separate block from the RTCC control and Configura-
tion registers. All SRAM locations are battery-backed-
up during a VCC power fail. Unused locations are not
accessible.
Addresses 0x00h-0x07h are the RTCC Time and
Date registers. These are read/write registers.
Care must be taken when writing to these
registers with the oscillator running.
Incorrect data can appear in the Time and Date
registers if a write is attempted during the time
frame where these internal registers are being
incremented. The user can minimize the
likelihood of data corruption by ensuring that any
writes to the Time and Date registers occur before
the contents of the second register reach a value
of 0x59H.
Addresses 0x08h-0x0Bh are the device Configu-
ration, Calibration, Watchdog Configuration and
Event Detect Configuration registers.
Addresses 0x0ch-0x11h are the Alarm 0 registers.
These are used to set up the Alarm 0, the
interrupt pin and the Alarm 0 compare.
Addresses 0x12h-0x17h are the Alarm 1
registers. These are used to set up the Alarm 1,
the interrupt pin and the Alarm 1 compare, Alarm
1 offers a enhanced resolution of tenth and
hundredths of seconds.
Addresses 0x18h-0x1Fh are used for the power-
down and power-up time-stamp feature. The
detailed memory map is shown in Table 4-1. No
error checking is provided when loading Time and
Date registers.
FIGURE 2-2:
MEMORY MAP
0x00
0x07
Time and Date
Configuration and Calibration
Alarm 0
Alarm 1
Time-Stamp
SRAM (64 Bytes)
0x09
0x0B
0x0C
0x11
0x12
0x17
0x18
0x1F
0x20
0x5F
0x00
EEPROM
Memory
0x00
0x07
0x08
0x0F
RTCC Register/SRAM
EEPROM
Unique ID Location 2
Unique ID Location 1
EUI-48/64
Unique ID
0xFF
Note: 1K EEPROM Max address is 0x7F.
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