參數(shù)資料
型號(hào)： MCP601
廠商： Microchip Technology Inc.
元件分類： FPGA
英文描述： 300000 SYSTEM GATE 2.5 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN
中文描述： 2.7V至5.5V單電源CMOS運(yùn)算放大器
文件頁(yè)數(shù)： 11/20頁(yè)
文件大?。?/td> 448K
代理商： MCP601
2000 Microchip Technology Inc.
DS21314D-page 11
MCP601/602/603/604
The maximum operating common-mode voltage that
can be applied to the inputs is V
SS
- 0.3V to V
DD
- 1.2V.
In contrast, the absolute maximum input voltage is V
SS
- 0.3V and V
DD
+ 0.3V. Voltages on the input that
exceed this absolute maximum rating can cause exces-
sive current to flow in or out of the input pins. Current
beyond ±2mA can cause possible reliability problems.
Applications that exceed this rating must be externally
limited with an input resistor as shown in Figure 3-3.
FIGURE 3-3:
Absolute Maximum Specifications, an input resistor,
R
IN
, should be used to limit the current flow into that
pin.
If the inputs of the amplifier exceed the
3.3
Capacitive Load and Stability
Driving capacitive loads can cause stability problems
with many of the higher speed amplifiers.
For any closed loop amplifier circuit, a good rule of
thumb is to design for a phase margin that is no less
than 45
°
. This is a conservative theoretical value, how-
ever, if the phase margin is lower, layout parasitics can
degrade the phase margin further causing a truly
unstable circuit. A system phase shift of 45
°
will have
an overshoot in its step response of approximately
25%.
A buffer configuration with a capacitive load is the most
difficult configuration for an amplifier to maintain stabil-
ity. The Phase versus Capacitive Load of the MCP60X
amplifier is shown in Figure 3-4. In this figure, it can be
seen that the amplifier has a phase margin above 40
°,
while driving capacitance loads up to 100pF.
FIGURE 3-4:
Capacitive Load
Gain Bandwidth, Phase Margin vs.
FIGURE 3-5:
when driving heavy capacitive loads.
Amplifier circuits that can be used
If the amplifier is required to drive larger capacitive
loads, the circuit shown in Figure 3-5 can be used. A
small series resistor (R
ISO
) at the output of the amplifier
improves the phase margin when driving large capaci-
tive loads. This resistor decouples the capacitive load
from the amplifier by introducing a zero in the transfer
function.
This zero adjusts the phase margin by approximately:
θ
m
= tan
-1
(2
π
GBWP x R
ISO
x C
L
)
where:
θ
m
is the improvement in phase margin,
GBWP
is the gain bandwidth product of the
amplifier,
R
ISO
is the capacitive decoupling resistor, and
C
L
is the load capacitance
R
IN
= (Maximum expected voltage - V
DD
) / 2mA
or
(V
SS
- Minimum expected voltage)/ 2mA.
R
IN
MCP60X
0
0.5
1
1.5
2
2.5
3
3.5
4
Capacitance (pF)
G
0
10
20
30
40
50
60
70
80
P
Gain-Bandwidth
Phase
Margin
V
DD
=5.0V,
R
L
=100 k
10 100 1E3 10E3 100E3 1E6
V
IN
C
L
R
ISO
V
OUT
MCP60X
V
DD
相關(guān)PDF資料
PDF描述
MCP601-I 2.7V to 5.5V Single Supply CMOS Op Amps
MCP601-IOT 2.7V to 5.5V Single Supply CMOS Op Amps
MCP601-IP 2.7V to 5.5V Single Supply CMOS Op Amps
MCP601-ISN 300000 SYSTEM GATE 2.5 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN
MCP601-IST 300000 SYSTEM GATE 2.5 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MCP601_04 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:2.7V to 5.5V Single-Supply CMOS Op Amps
MCP601_07 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:2.7V to 6.0V Single Supply CMOS Op Amps
MCP601-E/CH 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:2.7V to 5.5V Single-Supply CMOS Op Amps
MCP601-E/OT 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:2.7V to 5.5V Single-Supply CMOS Op Amps
MCP601-E/P 功能描述:運(yùn)算放大器 - 運(yùn)放 Single 2.7V RoHS:否 制造商:STMicroelectronics 通道數(shù)量:4 共模抑制比（最小值）:63 dB 輸入補(bǔ)償電壓:1 mV 輸入偏流（最大值）:10 pA 工作電源電壓:2.7 V to 5.5 V 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-16 轉(zhuǎn)換速度:0.89 V/us 關(guān)閉:No 輸出電流:55 mA 最大工作溫度:+ 125 C 封裝:Reel
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