參數(shù)資料
型號(hào): MCP4251-103E/SL
廠商: Microchip Technology
文件頁(yè)數(shù): 51/59頁(yè)
文件大小: 0K
描述: IC DGTL POT 10K 2CH 14SOIC
標(biāo)準(zhǔn)包裝: 57
接片: 257
電阻(歐姆): 10k
電路數(shù): 2
溫度系數(shù): 標(biāo)準(zhǔn)值 150 ppm/°C
存儲(chǔ)器類型: 易失
接口: 4 線 SPI(芯片選擇)
電源電壓: 1.8 V ~ 5.5 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 14-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 14-SOIC
包裝: 管件
產(chǎn)品目錄頁(yè)面: 676 (CN2011-ZH PDF)
其它名稱: MCP4251-103-E/SL
MCP4251-103-E/SL-ND
Micrel, Inc.
KSZ8051MNL/RNL
July 2010
55
M9999-070910-1.0
Reset Circuit
The following reset circuit is recommended for powering up the KSZ8051MNL/RNL if reset is triggered by the power
supply.
Figure 19. Recommended Reset Circuit
The following reset circuit is recommended for applications where reset is driven by another device (e.g., CPU or FPGA).
At power-on-reset, R, C and D1 provide the necessary ramp rise time to reset the KSZ8051MNL/RNL device. The
RST_OUT_n from CPU/FPGA provides the warm reset after power up.
Figure 20. Recommended Reset Circuit for interfacing with CPU/FPGA Reset Output.
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