VDD
參數資料
型號: MCP41050-E/SN
廠商: Microchip Technology
文件頁數: 24/28頁
文件大?。?/td> 0K
描述: IC POT DGTL 50K 1CH SPI 8SOIC
標準包裝: 100
接片: 256
電阻(歐姆): 50k
電路數: 1
溫度系數: 標準值 800 ppm/°C
存儲器類型: 易失
接口: 3 線串行(芯片選擇)
電源電壓: 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應商設備封裝: 8-SOICN
包裝: 管件
2003 Microchip Technology Inc.
DS11195C-page 5
MCP41XXX/42XXX
Absolute Maximum Ratings
VDD...................................................................................7.0V
All inputs and outputs w.r.t. VSS ............... -0.6V to VDD +1.0V
Storage temperature .....................................-60°C to +150°C
Ambient temp. with power applied ................-60°C to +125°C
ESD protection on all pins
..................................................≥ 2kV
Notice: Stresses above those listed under “maximum rat-
ings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied. Expo-
sure to maximum rating conditions for extended periods may
affect device reliability.
AC TIMING CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, VDD = +2.7V to 5.5V, TA = -40°C to +85°C.
Parameter
Sym
Min.
Typ.
Max.
Units
Conditions
Clock Frequency
FCLK
——
10
MHz
VDD = 5V (Note 1)
Clock High Time
tHI
40
ns
Clock Low Time
tLO
40
ns
CS Fall to First Rising CLK Edge
tCSSR
40
ns
Data Input Setup Time
tSU
40
ns
Data Input Hold Time
tHD
10
ns
SCK Fall to SO Valid Propagation Delay
tDO
—80
ns
CL = 30 pF (Note 2)
SCK Rise to CS Rise Hold Time
tCHS
30
ns
SCK Rise to CS Fall Delay
tCS0
10
ns
CS Rise to CLK Rise Hold
tCS1
100
ns
CS High Time
tCSH
40
ns
Reset Pulse Width
tRS
150
ns
RS Rising to CS Falling Delay Time
tRSCS
150
ns
CS rising to RS or SHDN falling delay time
tSE
40
ns
CS low time
tCSL
100
ns
Shutdown Pulse Width
tSH
150
ns
Note
1:
When using the device in the daisy-chain configuration, maximum clock frequency is determined by a combination of propagation delay
time (tDO) and data input setup time (tSU). Max. clock frequency is therefore ~ 5.8 MHz based on SCK rise and fall times of 5 ns, tHI =
40 ns, tDO = 80 ns and tSU = 40 ns.
2:
Applies only to the MCP42XXX devices.
3:
Applies only when using hardware pins to exit software shutdown mode, MCP42XXX only.
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