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參數(shù)資料
| 型號(hào)： | MCP3903T-I/SS |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 7/15頁 |
| 文件大小： | 0K |
| 描述： | IC AFE 24BIT 64KSPS 6CH 28SSOP |
| 產(chǎn)品培訓(xùn)模塊： | MCP3903 6-Channel Energy Measurement Analog Front End |
| 標(biāo)準(zhǔn)包裝： | 2,100 |
| 位數(shù)： | 24 |
| 通道數(shù)： | 6 |
| 電壓 - 電源，模擬： | 4.5 V ~ 5.5 V |
| 電壓 - 電源，數(shù)字： | 2.7 V ~ 3.6 V |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SSOP |
| 包裝： | 帶卷 (TR) |
2011 Microchip Technology Inc.
DS25048B-page 15
MCP3903
3.3
Analog VDD (AVDD)
AVDD is the power supply pin for the analog circuitry
within the MCP3903.
This pin requires appropriate bypass capacitors and
should be maintained to 5V ±10% for specified
operation.
3.4
ADC Differential Analog
Inputs(CHn+/CHn-)
CHn- and CHn+, are the two fully-differential analog
voltage inputs for the Delta-Sigma ADCs. There are six
channels in total grouped in three channel pairs.
The linear and specified region of the channels are
dependent on the PGA gain. This region corresponds
to a differential voltage range of ±500 mV/GAIN with
VREF = 2.4V. The maximum absolute voltage, with
respect to AGND, for each CHn+/- input pin is +/-1V
with no distortion and ±6V with no breaking after
continuous voltage.
3.5
Analog Ground (AGND)
AGND is the ground connection to internal analog
circuitry (ADCs, PGA, voltage reference, POR). To
ensure accuracy and noise cancellation, this pin must
be connected to the same ground as DGND, preferably
with a star connection. If an analog ground plane is
available, it is recommended that this pin be tied to this
plane of the PCB. This plane should also reference all
other analog circuitry in the system.
3.6
Non-Inverting Reference Input,
Internal Reference Output
(REFIN+/OUT)
This pin is the non-inverting side of the differential
voltage reference input for all ADCs or the internal
voltage reference output. When VREFEXT = 1, and an
external voltage reference source can be used, the
internal voltage reference is disabled. When using an
external differential voltage reference, it should be
connected to its VREF+ pin.
When using an external single-ended reference, it
should be connected to this pin.
When VREFEXT = 0, the internal voltage reference is
enabled and connected to this pin through a switch.
This voltage reference has minimal drive capability and
thus needs proper buffering and bypass capacitances
(10 μF tantalum in parallel with 0.1 μF ceramic) if used
as a voltage source.
For optimal performance, bypass capacitances should
be connected between this pin and AGND at all times
even when the internal voltage reference is used.
3.7
Inverting Reference Input (REFIN-)
This pin is the inverting side of the differential voltage
reference input for both ADCs. When using an external
differential voltage reference, it should be connected to
its VREF- pin. When using an external single-ended
voltage reference, or when VREFEXT = 0 (Default)
and using the internal voltage reference, this pin should
be directly connected to AGND.
3.8
Digital Ground Connection
(DGND)
DGND is the ground connection to internal digital
circuitry (SINC filters, oscillator, serial interface). To
ensure accuracy and noise cancellation, DGND must
be connected to the same ground as AGND, preferably
with a star connection. If a digital ground plane is
available, it is recommended that this pin be tied to this
plane of the Printed Circuit Board (PCB). This plane
should also reference all other digital circuitry in the
system.
3.9
DRn (Data Ready Pins)
The Data Ready pins indicate if a new conversion
result is ready to be read on each of the A, B and C
pairs of ADCs. The default state of this pin is high when
DR_HIZN=1 and is high impedance when DR_HIZN=0
(Default). After each conversion is finished, a low pulse
will take place on the data ready pins to indicate the
conversion result is ready as an interrupt. This pulse is
synchronous with the master clock and has a defined
and constant width.
The Data Ready pins are independent of the SPI
interface and act like an interrupt output.The Data
Ready pins state is not latched and the pulse width
(and period) are both determined by the MCLK
frequency, over-sampling rate, and internal clock pre-
scale settings. The DR pulse width is equal to one
DMCLK period and the frequency of the pulses is equal
to DRCLK (see Figure 1-3).
Note:
These pins should not be left floating
when DR_HIZ bit is low; a 100k pull-up
resistor connected to DVDD is recom-
mended.
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