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參數(shù)資料
| 型號： | MCP3426A0-E/MS |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 15/56頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT I2C PROGBL 8-MSOP |
| 產(chǎn)品培訓(xùn)模塊： | MCP3901 Analog Front End |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 15 |
| 數(shù)據(jù)接口： | I²C，串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-MSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個差分，單極 |
| 產(chǎn)品目錄頁面： | 672 (CN2011-ZH PDF) |
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MCP3426/7/8
DS22226A-page 22
2009 Microchip Technology Inc.
5.3.4
READING OUTPUT CODES AND
CONFIGURATION BYTE FROM THE
DEVICE
When the Master sends a read command (R/W = 1),
the device outputs both the conversion data and
configuration bytes. Each byte consists of 8 bits with
one acknowledge (ACK) bit. The ACK bit after the
address byte is issued by the device and the ACK bits
after each conversion data bytes are issued by the
Master.
When the device receives a read command, it outputs
two data bytes followed by a configuration register. In
16-bit conversion mode, the MSB (= sign bit) of the first
data byte is D15. In 14-bit conversion mode, the first
two bits in the first data byte are repeated MSB bits and
can be ignored, and the 3rd bit (D13) is the MSB (=sign
bit) of the conversion data. In 12-bit conversion mode,
the first four bits are repeated MSB bits and can be
ignored. The 5th bit (D11) of the byte represents the
MSB (= sign bit) of the conversion data. Table 5-4
summarizes the conversion data output of each
conversion mode.
The configuration byte follows the output data bytes.
The device repeatedly outputs the configuration byte
only if the Master sends clocks repeatedly after the
data bytes.
The device terminates the current outputs when it
receives a Not-Acknowledge (NAK) with a repeated
start or a stop bit at the end of each output byte. It is not
required to read the configuration byte. However, the
Master may read the configuration byte to check the
RDY bit condition.The Master may continuously send
clock (SCL) to repeatedly read the configuration byte
(to check the RDY bit status).
Figure 5-4 shows the timing diagram for reading the
ADC conversion data.
TABLE 5-4:
OUTPUT CODES OF EACH RESOLUTION OPTION
Conversion
Option
Digital Output Codes
16-bits
D15 ~ D8 (1st data byte) - D7 ~ D0 (2nd data byte) - Configuration byte. (Note 1)
14-bits
MMD13D ~ D8 (1st data byte) - D7 ~ D0 (2nd data byte) - Configuration byte. (Note 2)
12-bits
MMMMD11 ~ D8 (1st data byte) - D7 ~ D0 (2nd data byte) - Configuration byte. (Note 3)
Note 1:
D15 is MSB (= sign bit).
2:
D13 is MSB (= sign bit), M is repeated MSB of the data byte.
3:
D11 is MSB (= sign bit), M is repeated MSB of the data byte.
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