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  • 參數(shù)資料
    型號(hào): MCP3422A0T-E/MC
    廠商: Microchip Technology
    文件頁(yè)數(shù): 7/58頁(yè)
    文件大?。?/td> 0K
    描述: IC ADC 18BIT 3.75SPS 2CH 8-DFN
    產(chǎn)品培訓(xùn)模塊: MCP3901 Analog Front End
    標(biāo)準(zhǔn)包裝: 3,300
    位數(shù): 18
    采樣率(每秒): 3.75
    數(shù)據(jù)接口: I²C,串行
    轉(zhuǎn)換器數(shù)目: 1
    電壓電源: 單電源
    工作溫度: -40°C ~ 125°C
    安裝類型: 表面貼裝
    封裝/外殼: 8-VFDFN 裸露焊盤
    供應(yīng)商設(shè)備封裝: 8-DFN(2x3)
    包裝: 帶卷 (TR)
    輸入數(shù)目和類型: 4 個(gè)單端,雙極;2 個(gè)差分,雙極
    配用: MCP3422EV-ND - BOARD EVAL MCP3422 PICKIT SERIAL
    其它名稱: MCP3422A0T-E/MCTR
    2009 Microchip Technology Inc.
    DS22088C-page 15
    MCP3422/3/4
    4.9
    Digital Output Codes and
    Conversion to Real Values
    4.9.1
    DIGITAL OUTPUT CODE FROM
    DEVICE
    The digital output code is proportional to the input
    voltage and PGA settings. The output data format is a
    binary two’s complement. With this code scheme, the
    MSB can be considered a sign indicator. When the
    MSB is a logic ‘0’, the input is positive. When the MSB
    is a logic ‘1’, the input is negative. The following is an
    example of the output code:
    a.
    for a negative full scale input voltage: 100...000
    Example: (CHn+ - CHn-)
    PGA = -2.048V
    b.
    for a zero differential input voltage: 000...000
    Example: (CHn+ - CHn-) = 0
    c.
    for a positive full scale input voltage: 011...111
    Example: (CHn+ - CHn-)
    PGA = 2.048V
    The MSB (sign bit) is always transmitted first through
    the I2C serial data line. The resolution for each
    conversion is 18, 16, 14, or 12 bits depending on the
    conversion rate selection bit settings by the user.
    The output codes will not roll-over even if the input
    voltage exceeds the maximum input range. In this
    case, the code will be locked at 0111...11 for all
    voltages greater than (VREF - 1 LSB)/PGA and
    1000...00
    for
    voltages
    less
    than
    -VREF/PGA.
    Table 4-2 shows an example of output codes of various
    input levels for 18 bit conversion mode. Table 4-3
    shows an example of minimum and maximum output
    codes for each conversion rate option.
    The number of output code is given by:
    EQUATION 4-2:
    The LSB of the data conversion is given by:
    EQUATION 4-3:
    Table 4-1 shows the LSB size of each conversion rate
    setting. The measured unknown input voltage is
    obtained by multiplying the output codes with LSB. See
    the following section for the input voltage calculation
    using the output codes.
    TABLE 4-1:
    RESOLUTION SETTINGS VS.
    LSB
    TABLE 4-2:
    EXAMPLE OF OUTPUT CODE
    FOR 18 BITS (NOTE 1, NOTE 2)
    TABLE 4-3:
    MINIMUM AND MAXIMUM
    OUTPUT CODES (NOTE)
    Number of Output Code =
    Maximum Code
    1
    +
    () PGA
    CHn+
    CHn-
    ()
    2.048V
    -----------------------------------------
    ×
    =
    Where:
    See Table 4-3 for Maximum Code
    LSB
    2V
    REF
    ×
    2
    N
    ----------------------
    2
    2.048V
    ×
    2
    N
    --------------------------
    ==
    Where:
    N
    =
    Resolution, which is programmed in
    the Configuration Register.
    Resolution Setting
    LSB
    12 bits
    1 mV
    14 bits
    250 V
    16 bits
    62.5 V
    18 bits
    15.625 V
    Input Voltage:
    [CHn+ - CHn-] PGA
    Digital Output Code
    V
    REF
    011111111111111111
    VREF - 1 LSB
    011111111111111111
    2LSB
    000000000000000010
    1LSB
    000000000000000001
    0
    000000000000000000
    -1 LSB
    111111111111111111
    -2 LSB
    111111111111111110
    - VREF
    100000000000000000
    < -VREF
    100000000000000000
    Note 1:
    MSB is a sign indicator:
    0: Positive input (CHn+ > CHn-)
    1: Negative input (CHn+ < CHn-)
    2:
    Output data format is binary two’s
    complement.
    Resolution
    Setting
    Data Rate
    Minimum
    Code
    Maximum
    Code
    12
    240 SPS
    -2048
    2047
    14
    60 SPS
    -8192
    8191
    16
    15 SPS
    -32768
    32767
    18
    3.75 SPS
    -131072
    131071
    Note:
    Maximum n-bit code = 2N-1 - 1
    Minimum n-bit code = -1 x 2N-1
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