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參數(shù)資料
| 型號(hào)： | MCP3421A5T-E/OT |
| 廠商： | Microchip Technology |
| 文件頁(yè)數(shù)： | 10/30頁(yè) |
| 文件大小： | 0K |
| 描述： | IC ADC 18BIT 3.75SPS SOT23-6 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 18 |
| 采樣率（每秒）： | 3.75 |
| 數(shù)據(jù)接口： | I²C，串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-6 |
| 供應(yīng)商設(shè)備封裝： | SOT-23-6 |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸入數(shù)目和類型： | 2 個(gè)單端，雙極；1 個(gè)差分，單極 |
| 配用： | MCP3421EV-ND - BOARD EVAL FOR MCP3421 SOT23-6 |
| 其它名稱： | MCP3421A5T-E/OTDKR |
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MCP3421
DS22003B-page 18
2006 Microchip Technology Inc.
TABLE 5-4:
I2C SERIAL TIMING SPECIFICATIONS
Electrical Specifications: Unless otherwise specified, all limits are specified for TA = -40 to +85°C, VDD = +2.7V, +3.3V or +5.0V,
VSS = 0V, VIN+ = VIN- = VREF/2.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Standard Mode
Clock frequency
fSCL
0
—
100
kHz
Clock high time
THIGH
4000
—
ns
Clock low time
TLOW
4700
—
ns
SDA and SCL rise time (Note 1)
TR
—
1000
ns
From VIL to VIH
SDA and SCL fall time (Note 1)
TF
—
300
ns
From VIH to VIL
START condition hold time
THD:STA
4000
—
ns
After this period, the first clock
pulse is generated.
Repeated START condition
setup time
TSU:STA
4700
—
ns
Only relevant for repeated Start
condition
Data hold time (Note 3)
THD:DAT
0
—
3450
ns
Data input setup time
TSU:DAT
250
—
ns
STOP condition setup time
TSU:STO
4000
—
ns
STOP condition hold time
THD:STD
4000
—
ns
Output valid from clock
TAA
0
—
3750
ns
Bus free time
TBUF
4700
—
ns
Time between START and STOP
conditions.
Fast Mode
Clock frequency
TSCL
0
—
400
kHz
Clock high time
THIGH
600
—
ns
Clock low time
TLOW
1300
—
ns
SDA and SCL rise time (Note 1)
TR
20 + 0.1Cb
—
300
ns
From VIL to VIH
SDA and SCL fall time (Note 1)
TF
20 + 0.1Cb
—
300
ns
From VIH to VIL
START condition hold time
THD:STA
600
—
ns
After this period, the first clock
pulse is generated
Repeated START condition
setup time
TSU:STA
600
—
ns
Only relevant for repeated Start
condition
Data hold time (Note 4)
THD:DAT
0
—
900
ns
Data input setup time
TSU:DAT
100
—
ns
STOP condition setup time
TSU:STO
600
—
ns
STOP condition hold time
THD:STD
600
—
ns
Output valid from clock
TAA
0
—
1200
ns
Bus free time
TBUF
1300
—
ns
Time between START and STOP
conditions.
Input filter spike suppression
TSP
0
—
50
ns
SDA and SCL pins
Note 1:
This parameter is ensured by characterization and not 100% tested.
2:
This specification is not a part of the I2C specification. This specification is equivalent to the Data Hold Time (THD:DAT)
plus SDA Fall (or rise) time: TAA = THD:DAT + TF (OR TR).
3:
If this parameter is too short, it can create an unintended Start or Stop condition to other devices on the bus line. If this
parameter is too long, Clock Low time (TLOW) can be affected.
4:
For Data Input: This parameter must be longer than tSP. If this parameter is too long, the Data Input Setup (TSU:DAT) or
Clock Low time (TLOW) can be affected.
For Data Output: This parameter is characterized, and tested indirectly by testing TAA parameter.
5:
This parameter is ensured by characterization and not 100% tested. This parameter is not available for Standard Mode.
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