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參數(shù)資料
| 型號(hào)： | MCP3421A2T-E/CH |
| 廠商： | Microchip Technology |
| 文件頁(yè)數(shù)： | 34/42頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 18BIT 3.75SPS 1CH SOT23-6 |
| 產(chǎn)品培訓(xùn)模塊： | MCP3901 Analog Front End |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 18 |
| 采樣率（每秒）： | 3.75 |
| 數(shù)據(jù)接口： | I²C，串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-6 |
| 供應(yīng)商設(shè)備封裝： | SOT-23-6 |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸入數(shù)目和類型： | 2 個(gè)單端，雙極；1 個(gè)差分，單極 |
| 產(chǎn)品目錄頁(yè)面： | 672 (CN2011-ZH PDF) |
| 其它名稱： | MCP3421A2T-E/CHDKR |
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MCP3421
DS22003E-page 4
2009 Microchip Technology Inc.
Gain Error
—
0.05
0.35
%
PGA = 1, DR = 3.75 SPS
PGA Gain Error Match
—
0.1
—
%
Between any 2 PGA gains
Gain Error Drift
—
15
—
ppm/°C
PGA=1, DR=3.75 SPS
Offset Error
VOS
—
15
40
V
Tested at PGA = 1
VDD = 5.0V and DR = 3.75 SPS
Offset Drift vs. Temperature
—
50
—
nV/°C
VDD = 5.0V
Common-Mode Rejection
—
105
—
dB
at DC and PGA =1,
—
110
—
dB
at DC and PGA =8,
TA = +25°C
Gain vs. VDD
—
5
—
ppm/V
TA = +25°C, VDD = 2.7V to 5.5V,
PGA = 1
Power Supply Rejection at DC
—
100
—
dB
TA = +25°C, VDD = 2.7V to 5.5V,
PGA = 1
Power Requirements
Voltage Range
VDD
2.7
—
5.5
V
Supply Current during
Conversion
IDDA
—
155
190
A
VDD = 5.0V
—
145
—
A
Supply Current during Standby
Mode
IDDS
—0.1
0.5
A
I2C Digital Inputs and Digital Outputs
High level input voltage
VIH
0.7 VDD
—VDD
V
Low level input voltage
VIL
—
0.3VDD
V
Low level output voltage
VOL
——
0.4
V
IOL = 3 mA, VDD = +5.0V
Hysteresis of Schmitt Trigger
for inputs
VHYST
0.05VDD
——
V
fSCL = 100 kHz
Supply Current when I2C bus
line is active
IDDB
——
10
A
Input Leakage Current
IILH
——
1
A
VIH = 5.5V
IILL
-1
—
A
VIL = GND
Pin Capacitance and I2C Bus Capacitance
Pin capacitance
CPIN
—
10
pF
I2C Bus Capacitance
Cb
—
400
pF
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all parameters apply for T
A = -40°C to +85°C, VDD = +5.0V, VSS = 0V,
VIN+ = VIN- = VREF/2. All ppm units use 2*VREF as full scale range.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Note 1:
Any input voltage below or greater than this voltage causes leakage current through the ESD diodes at the input pins.
This parameter is ensured by characterization and not 100% tested.
2:
This input impedance is due to 3.2 pF internal input sampling capacitor.
3:
The total conversion speed includes auto-calibration of offset and gain.
4:
INL is the difference between the endpoints line and the measured code at the center of the quantization band.
5:
Includes all errors from on-board PGA and VREF.
6:
Full Scale Range (FSR) = 2 x 2.048/PGA = 4.096/PGA.
7:
This parameter is ensured by characterization and not 100% tested.
8:
This parameter is ensured by design and not 100% tested.
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