FIGURE 1-1: Standard and Fast Mode Bus Timing Data.
參數資料
型號: MCP3221A7T-E/OT
廠商: Microchip Technology
文件頁數: 23/28頁
文件大?。?/td> 0K
描述: ADC 12BIT I2C INTERFACE SOT23-5
標準包裝: 1
位數: 12
采樣率(每秒): 22.3k
數據接口: I²C,串行
轉換器數目: 1
電壓電源: 單電源
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: SC-74A,SOT-753
供應商設備封裝: SOT-23-5
包裝: 標準包裝
輸入數目和類型: 1 個單端,單極
其它名稱: MCP3221A7T-E/OTDKR
MCP3221
DS21732C-page 4
2006 Microchip Technology Inc.
TIMING SPECIFICATIONS
FIGURE 1-1:
Standard and Fast Mode Bus Timing Data.
Electrical Characteristics: All parameters apply at VDD = 2.7V - 5.5V, VSS = GND, TAMB = -40°C to +85°C.
Parameters
Sym
Min
Typ
Max
Units
Conditions
I2C Standard Mode
Clock frequency
fSCL
0
100
kHz
Clock high time
THIGH
4000
ns
Clock low time
TLOW
4700
ns
SDA and SCL rise time
TR
1000
ns
From VIL to VIH (Note 1)
SDA and SCL fall time
TF
300
ns
From VIL to VIH (Note 1)
START condition hold time
THD:STA
4000
ns
START condition setup time
TSU:STA
4700
ns
Data input setup time
TSU:DAT
250
ns
STOP condition setup time
TSU:STO
4000
ns
STOP condition hold time
THD:STD
4000
ns
Output valid from clock
TAA
3500
ns
Bus free time
TBUF
4700
ns
Input filter spike suppression
TSP
50
ns
SDA and SCL pins (Note 1)
I2C Fast Mode
Clock frequency
FSCL
0
400
kHz
Clock high time
THIGH
600
ns
Clock low time
TLOW
1300
ns
SDA and SCL rise time
TR
20 + 0.1CB
300
ns
From VIL to VIH (Note 1)
SDA and SCL fall time
TF
20 + 0.1CB
300
ns
From VIL to VIH (Note 1)
START condition hold time
THD:STA
600
ns
START condition setup time
TSU:STA
600
ns
Data input hold time
THD:DAT
0—
0.9
ms
Data input setup time
TSU:DAT
100
ns
STOP condition setup time
TSU:STO
600
ns
STOP condition hold time
THD:STD
600
ns
Output valid from clock
TAA
900
ns
Bus free time
TBUF
1300
ns
Input filter spike suppression
TSP
50
ns
SDA and SCL pins (Note 1)
Note 1:
This parameter is periodically sampled and not 100% tested.
2:
Time the bus must be free before a new transmission can start.
TF
THIGH
VHYS
TR
TSU:STA
TSP
THD:STA
TLOW
THD:DAT
TSU:DAT
TSU:STO
TBUF
TAA
SCL
SDA
IN
SDA
OUT
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