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| 型號： | MCP3204T-CI/SL |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 14/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 2.7V 4CH SPI 14SOIC |
| 標準包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 100k |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 14-SOIC |
| 包裝： | 標準包裝 |
| 輸入數(shù)目和類型： | 4 個單端，單極；2 個偽差分，單極 |
| 產品目錄頁面： | 672 (CN2011-ZH PDF) |
| 其它名稱： | MCP3204T-CI/SLDKR |
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2008 Microchip Technology Inc.
DS21298E-page 21
MCP3204/3208
6.0
APPLICATIONS INFORMATION
6.1
Using the MCP3204/3208 with
Microcontroller (MCU) SPI Ports
With most microcontroller SPI ports, it is required to
send groups of eight bits. It is also required that the
microcontroller SPI port be configured to clock out data
on the falling edge of clock and latch data in on the
rising edge. Because communication with the
MCP3204/3208 devices may not need multiples of
eight clocks, it will be necessary to provide more clocks
than are required. This is usually done by sending
‘leading zeros’ before the start bit. As an example,
Figure 6-1 and Figure 6-2 illustrate how the MCP3204/
3208 can be interfaced to a MCU with a hardware SPI
port. Figure 6-1 depicts the operation shown in SPI
Mode 0,0, which requires that the SCLK from the MCU
idles in the ‘low’ state, while Figure 6-2 shows the
similar case of SPI Mode 1,1, where the clock idles in
the ‘high’ state.
As is shown in Figure 6-1, the first byte transmitted to
the A/D converter contains five leading zeros before
the start bit. Arranging the leading zeros this way
allows the output 12 bits to fall in positions easily
manipulated by the MCU. The MSB is clocked out of
the A/D converter on the falling edge of clock number
12. Once the second eight clocks have been sent to the
device, the MCU’s receive buffer will contain three
unknown bits (the output is at high impedance for the
first two clocks), the null bit and the highest order four
bits of the conversion. Once the third byte has been
sent to the device, the receive register will contain the
lowest order eight bits of the conversion results.
Employing this method ensures simpler manipulation
of the converted data.
Figure 6-2 shows the same thing in SPI Mode 1,1,
which requires that the clock idles in the high state. As
with mode 0,0, the A/D converter outputs data on the
falling edge of the clock and the MCU latches data from
the A/D converter in on the rising edge of the clock.
FIGURE 6-1:
SPI Communication using 8-bit segments (Mode 0,0: SCLK idles low).
1
2
34
5
678
9
10 11 12 13 14 15 16
CS
SCLK
DIN
X = “Don’t Care” Bits
17 18 19 20 21 22 23 24
DOUT
NULL
BIT B11 B10 B9 B8
B7
B6 B5 B4 B3 B2 B1 B0
HI-Z
MCU latches data from A/D
Data is clocked out of A/D
converter on falling edges
converter on rising edges of SCLK
DO
Don’t Care
SGL/
DIFF
D1
D2
Start
00
0
1
XX
X
DO
XX
X
B7
B6
B5
B4 B3
B2
B1
B0
B11 B10 B9
B8
0
?
????
???
D1
D2
SGL/
DIFF
Start
Bit
(Null)
MCU Transmitted Data
(Aligned with falling
edge of clock)
MCU Received Data
(Aligned with rising
edge of clock)
X
Data stored into MCU receive
register after transmission of first
8 bits
Data stored into MCU receive
register after transmission of
second 8 bits
Data stored into MCU receive
register after transmission of last
8 bits
Don’t Care
00
0
1
XX
X
DO
XX
X
B7 B6 B5 B4 B3 B2 B1 B0
B11 B10 B9 B8
0
?
????
???
D1
D2
SGL/
DIFF
(Null)
X
23
B1
X
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