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參數(shù)資料
| 型號： | MCP3201-CI/SN |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 16/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT SINGLE CHAN 8SOIC |
| 標準包裝： | 100 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 100k |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 8-SOICN |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個單端，單極 |
| 產(chǎn)品目錄頁面： | 672 (CN2011-ZH PDF) |
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1998-2011 Microchip Technology Inc.
DS21290F-page 23
MCP3201
6.4
Layout Considerations
When laying out a printed circuit board for use with
analog components, care should be taken to reduce
noise wherever possible. A bypass capacitor should
always be used with this device and should be placed
as close as possible to the device pin. A bypass
capacitor value of 1 F is recommended.
Digital and analog traces should be separated as much
as possible on the board and no traces should run
underneath the device or the bypass capacitor. Extra
precautions should be taken to keep traces with high-
frequency signals (such as clock lines) as far as
possible from analog traces.
Use of an analog ground plane is recommended in
order to keep the ground potential the same for all
devices on the board. Providing V
DD connections to
devices in a “star” configuration can also reduce noise
by eliminating current return paths and associated
errors. See Figure 6-4. For more information on layout
tips when using A/D Converter, refer to AN688 “Layout
Tips for 12-Bit A/D Converter Applications”
.
FIGURE 6-4:
VDD traces arranged in a
‘Star’ configuration in order to reduce errors
caused by current return paths.
VDD
Connection
Device 1
Device 2
Device 3
Device 4
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