參數(shù)資料
型號: MCIMX353CJQ5CR2
廠商: Freescale Semiconductor
文件頁數(shù): 24/147頁
文件大?。?/td> 0K
描述: MULTIMEDIA PROCESSOR 400-MAPBGA
標準包裝: 90
系列: i.MX35
核心處理器: ARM11
芯體尺寸: 32-位
速度: 532MHz
連通性: 1 線,CAN,EBI/EMI,以太網(wǎng),I²C,MMC,SPI,SSI,UART/USART,USB OTG
外圍設備: DMA,I²S,LCD,POR,PWM,WDT
輸入/輸出數(shù): 96
程序存儲器類型: ROMless
RAM 容量: 128K x 8
電壓 - 電源 (Vcc/Vdd): 1.33 V ~ 1.47 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 400-LFBGA
包裝: 帶卷 (TR)
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor
12
3
Signal Descriptions: Special Function Related Pins
Some special functional requirements are supported in the device. The details about these special functions
and the corresponding pin names are listed in Table 5.
4
Electrical Characteristics
The following sections provide the device-level and module-level electrical characteristics for the i.MX35
processor.
4.1
i.MX35 Chip-Level Conditions
This section provides the device-level electrical characteristics for the IC. See Table 6 for a quick reference
to the individual tables and sections.
1 ARM = ARM1136 platform, SDMA = SDMA platform
Table 5. Special Function Related Pins
Function Name
Pin Name
Mux Mode
Detailed Description
External ARM Clock
EXT_ARMCLK
ALT0
External clock input for ARM clock.
External Peripheral Clock
I2C1_CLK
ALT6
External peripheral clock source.
External 32-kHz Clock
CAPTURE
ALT4
External clock input of 32 kHz, used when the internal
24M Oscillator is powered off, which could be
configured either from CAPTURE or CSPI1_SS1.
CSPI1_SS1
ALT2
Clock Out
CLKO
ALT0
Clock-out pin from CCM, clock source is controllable
and can also be used for debug.
Power Ready
GPIO1_0
ALT1
PMIC power-ready signal, which can be configured
either from GPIO1_0 or TX1.
TX1
ALT1
Tamper Detect
GPIO1_1
ALT6
Tamper-detect logic is used to issue a security
violation. This logic is activated if the tamper-detect
input is asserted. Tamper-detect logic is enabled by the
bit of IOMUXC_GPRA[2]. After enabling the logic, it is
impossible to disable it until the next reset.
Table 6. i.MX35 Chip-Level Conditions
Characteristics
Table/Location
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