參數(shù)資料
型號(hào)： MCHC812A4PV8
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： Microcontrollers
中文描述： 微控制器
文件頁(yè)數(shù)： 215/242頁(yè)
文件大?。?/td> 1285K
代理商： MCHC812A4PV8
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Background Debug Mode (BDM)
MC68HC812A4 Data Sheet, Rev. 7
Freescale Semiconductor
215
BDM becomes active at the next instruction boundary following execution of the BDM BACKGROUND
command, but tags activate BDM before a tagged instruction is executed.
In special single-chip mode, background operation is enabled and active immediately out of reset. This
active case replaces the M68HC11 boot function and allows programming a system with blank memory.
While BDM is active, a set of BDM control registers are mapped to addresses $FF00 to $FF06. The BDM
control logic uses these registers which can be read anytime by BDM logic, not user programs. Refer to
17.4 BDM Registers
for detailed descriptions.
Some on-chip peripherals have a BDM control bit which allows suspending the peripheral function during
BDM. For example, if the timer control is enabled, the timer counter is stopped while in BDM. Once normal
program flow is continued, the timer counter is re-enabled to simulate real-time operations.
17.3.3 BDM Commands
All BDM command opcodes are eight bits long and can be followed by an address and/or data, as
indicated by the instruction. These commands do not require the CPU to be in active BDM mode for
execution.
The host controller must wait 150 cycles for a non-intrusive BDM command to execute before another
command can be sent. This delay includes 128 cycles for the maximum delay for a dead cycle. For data
read commands, the host must insert this delay between sending the address and attempting to read the
data.
BDM logic retains control of the internal buses until a read or write is completed. If an operation can be
completed in a single cycle, it does not intrude on normal CPU operation. However, if an operation
requires multiple cycles, CPU clocks are frozen until the operation is complete.
The CPU must be in background mode to execute commands that are implemented in the BDM ROM.
The BDM ROM is located at $FF20 to $FFFF while BDM is active. There are also seven bytes of BDM
registers which are located at $FF00 to $FF06 while BDM is active. The CPU executes code from this
ROM to perform the requested operation. These commands are shown in
Table 17-2
and
Table 17-3
.
Table 17-2. BDM Commands Implemented in Hardware
Command
Opcode (Hex)
Data
Description
BACKGROUND
90
None
Enter background mode, if firmware is enabled.
READ_BD_BYTE
E4
16-bit address
16-bit data out
Read from memory with BDM in map (may steal cycles if
external access); data for odd address on low byte, data for
even address on high byte
STATUS
(1)
E4
FF01,
0000 0000 (out)
READ_BD_BYTE $FF01. Running user code; BGND
instruction is not allowed
FF01,
1000 0000 (out)
READ_BD_BYTE $FF01. BGND instruction is allowed.
FF01,
1100 0000 (out)
READ_BD_BYTE $FF01. Background mode active,
waiting for single wire serial command
READ_BD_WORD
EC
16-bit address
16-bit data out
Read from memory with BDM in map (may steal cycles if
external access); must be aligned access
READ_BYTE
E0
16-bit address
16-bit data out
Read from memory with BDM out of map (may steal cycles
if external access); data for odd address on low byte, data
for even address on high byte
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