Figure 27. I
參數(shù)資料
型號(hào)： MCF54418CMJ250
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 42/61頁(yè)
文件大?。?/td> 0K
描述： IC MCU 32BIT 256MAPBGA
標(biāo)準(zhǔn)包裝： 450
系列： MCF5441x
核心處理器： Coldfire V4
芯體尺寸： 32-位
速度： 250MHz
連通性： 1 線，CAN，EBI/EMI，以太網(wǎng)，I²C，智能卡，SPI，SSI，UART/USART，USB，USB OTG
外圍設(shè)備： DMA，PWM，WDT
輸入/輸出數(shù)： 87
程序存儲(chǔ)器類(lèi)型： ROMless
RAM 容量： 64K x 8
電壓 - 電源 (Vcc/Vdd)： 1.14 V ~ 1.32 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b，D/A 2x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 256-LBGA
包裝： 托盤(pán)
Electrical characteristics
MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
47
Figure 27. I2C input/output timings
4.22
Ethernet assembly timing specifications
The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing
specs/constraints for the physical interface.
All Ethernet signals use pad type pad_fsr. The following timing specifications assume a pad slew rate setting of 11 and a load
of 50 pF.1
Table 30. I2C output timing specifications between SCL and SDA
Num
Characteristic
Min
Max
Units
I11
1 Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum
frequency (IFDR = 0x20) results in minimum output timings as shown in Table 30. The I2C interface is
designed to scale the actual data transition time to move it to the middle of the SCL low period. The actual
position is affected by the prescale and division values programmed into the IFDR. However, the numbers
given in Table 30 are minimum values.
Start condition hold time
6
—
1/fSYS
I21
Clock low period
10
—
1/fSYS
I32
2 Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only actively drive
low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external signal capacitance and
pull-up resistor values.
I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH =2.4 V)
—
s
I41
Data hold time
7
—
1/fSYS
I53
3 Specified at a nominal 50-pF load.
I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V)
—
3
ns
I61
Clock high time
10
—
1/fSYS
I71
Data setup time
2
—
1/fSYS
I81
Start condition setup time (for repeated start condition only)
20
—
1/fSYS
I91
Stop condition setup time
10
—
1/fSYS
1.These timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting
(11). When operating this interface at lower frequencies, increase the slew rate by using the 10, 01, or 00 setting to
increase edge rise and fall times, thus reducing EMI.
I2
I6
I1
I4
I7
I8
I9
I5
I3
I2C_SCL
I2C_SDA
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