參數(shù)資料
型號: MCF5407CFT162
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 162 MHz, RISC PROCESSOR, PQFP208
封裝: 28 X 28 MM, 0.50 MM PITCH, PLASTIC, FQFP-208
文件頁數(shù): 30/35頁
文件大?。?/td> 441K
代理商: MCF5407CFT162
4
MCF5407 Integrated ColdFire Microprocessor Product Brief
MOTOROLA
MCF5407 Features
— Two independent decoupled pipelines: four-stage instruction fetch pipeline (IFP) and
five-stage operand execution pipeline (OEP)
— Ten-instruction FIFO buffer provides decoupling between the pipelines
— Limited superscalar design achieves performance levels close to dual-issue performance
— Programmable two-level branch acceleration mechanism with an 8-entry branch cache plus a
128-entry prediction table for increased performance
— 32-bit internal address bus supporting 4 Gbytes of linear address space
— 32-bit data bus
— 16 user-accessible, 32-bit-wide, general-purpose registers
— Supervisor/user modes for system protection
— Vector base register to relocate exception-vector table
— Optimized for high-level language constructs
Multiply and accumulate unit (MAC)
— Provides high-speed, complex arithmetic processing for DSP applications
— Tightly coupled to the OEP
— Three-stage execute pipeline with one clock issue rate for 16 x 16 operations
— Supports 16 x 16 and 32 x 32 multiplies, all with 32-bit accumulate
— Supports signed or unsigned integers, plus signed fractional operands
Hardware integer divide unit
— Supports unsigned and signed integer divides
— Tightly coupled to the OEP
— Supports 32/16, and 32/32 operations producing quotient and/or remainder results
16-Kbyte instruction cache, 8-Kbyte data cache
— Four-way set-associative organization
— Operates at higher processor core frequency
— Provides pipelined, single-cycle access to critical code and data
— Data cache supports write-through and copyback modes
— Four-entry, 32-bit store buffer to improve performance of operand writes
Two, 2-Kbyte SRAMs
— Programmable location anywhere within 4-Gbyte linear address space
— Operates at higher core frequency
— Provides pipelined, single-cycle access to critical code and/or data
— Each block can be mapped to either the instruction or data operand bus
DMA controller
— Four fully-programmable channels: two support external requests and external acknowledges
— Supports dual-address and single-address transfers with 8-, 16-, and 32-bit data capability
— Source/destination address pointers that can increment or remain constant
— 24-bit transfer counter per channel
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