MCF537x ColdFire Microprocessor Data Sheet, Rev. 4 Pin Assignments and Reset Sta" />
參數(shù)資料
型號(hào)： MCF5372LCVM240J
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 43/46頁(yè)
文件大小： 0K
描述： IC MPU RISC 240MHZ 196MABGA
標(biāo)準(zhǔn)包裝： 126
系列： MCF537x
核心處理器： Coldfire V3
芯體尺寸： 32-位
速度： 240MHz
連通性： EBI/EMI，以太網(wǎng)，I²C，SPI，SSI，UART/USART，USB，USB OTG
外圍設(shè)備： DMA，POR，PWM，WDT
輸入/輸出數(shù)： 62
程序存儲(chǔ)器類型： ROMless
RAM 容量： 32K x 8
電壓 - 電源 (Vcc/Vdd)： 1.4 V ~ 3.6 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 196-LBGA
包裝： 托盤
MCF537x ColdFire Microprocessor Data Sheet, Rev. 4
Pin Assignments and Reset States
Freescale Semiconductor
6
high current in the internal ESD protection diodes. The rise times on the power supplies should be slower than 500 us to avoid
turning on the internal ESD protection clamp diodes.
3.3.2
Power Down Sequence
If IVDD/PLLVDD are powered down first, sense circuits in the I/O pads cause all output drivers to be in a high impedance state.
There is no limit on how long after IVDD and PLLVDD power down before EVDD or SDVDD must power down. IVDD should
not lag EVDD, SDVDD, or PLLVDD going low by more than 0.4 V during power down or there is undesired high current in the
ESD protection diodes. There are no requirements for the fall times of the power supplies.
The recommended power down sequence is as follows:
1.
Drop IVDD/PLLVDD to 0 V.
2.
Drop EVDD/SDVDD supplies.
4
Pin Assignments and Reset States
4.1
Signal Multiplexing
The following table lists all the MCF537x pins grouped by function. The Dir column is the direction for the primary function
of the pin only. Refer to Section 7, “Package Information,” for package diagrams. For a more detailed discussion of the
MCF537x signals, consult the MCF5373 Reference Manual (MCF5373RM).
NOTE
In this table and throughout this document, a single signal within a group is designated
without square brackets (i.e., A23), while designations for multiple signals within a group
use brackets (i.e., A[23:21]) and is meant to include all signals within the two bracketed
numbers when these numbers are separated by a colon.
NOTE
The primary functionality of a pin is not necessarily its default functionality. Pins that are
muxed with GPIO default to their GPIO functionality.
Table 3. MCF5372/3 Signal Information and Muxing
Signal Name
GPIO
Alternate 1
Alternate 2
Dir
.1
Vo
lt
a
g
e
Doma
in
MCF5372
MCF5373
160 QFP
MCF5372L
MCF53721
MCF5373L
196 MAPBGA
Reset
RESET2
—
I
EVDD
95
K13
RSTOUT
—
O
EVDD
86
L12
Clock
EXTAL
—
I
EVDD
91
L14
XTAL2
—
O
EVDD
93
K14
EXTAL32K
—
I
EVDD
—
P13
XTAL32K
—
O
EVDD
—
N13
FB_CLK
—
O
SDVDD
40
N1
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MCF53721CVM240,
MCF5372LCVM240,
MCF5373LCVM240
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