參數(shù)資料
型號(hào): MCF5372CAB180
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 180 MHz, RISC PROCESSOR, PQFP160
封裝: 28 X 28 MM, ROHS COMPLIANT, PLASTIC, QFP-160
文件頁(yè)數(shù): 21/46頁(yè)
文件大小: 922K
代理商: MCF5372CAB180
MCF537x ColdFire Microprocessor Data Sheet, Rev. 4
Electrical Characteristics
Freescale Semiconductor
28
5.10
USB On-The-Go
The MCF5373 device is compliant with industry standard USB 2.0 specification.
5.11
SSI Timing Specifications
This section provides the AC timings for the SSI in master (clocks driven) and slave modes (clocks input). All timings are given
for non-inverted serial clock polarity (SSI_TCR[TSCKP] = 0, SSI_RCR[RSCKP] = 0) and a non-inverted frame sync
(SSI_TCR[TFSI] = 0, SSI_RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timings
remain valid by inverting the clock signal (SSI_BCLK) and/or the frame sync (SSI_FS) shown in the figures below.
Table 14. SSI Timing – Master Modes1
1 All timings specified with a capactive load of 25pF.
Num
Description
Symbol
Min
Max
Units
S1
SSI_MCLK cycle time2
2 SSI_MCLK can be generated from SSI_CLKIN or a divided version of the internal system clock
(SYSCLK).
tMCLK
8
× t
SYS
—ns
S2
SSI_MCLK pulse width high / low
45%
55%
tMCLK
S3
SSI_BCLK cycle time3
3 SSI_BCLK can be derived from SSI_CLKIN or a divided version of SYSCLK. If the SYSCLK is used, the
minimum divider is 6. If the SSI_CLKIN input is used, the programmable dividers must be set to ensure
that SSI_BCLK does not exceed 4 x fSYS.
tBCLK
8
× t
SYS
—ns
S4
SSI_BCLK pulse width
45%
55%
tBCLK
S5
SSI_BCLK to SSI_FS output valid
15
ns
S6
SSI_BCLK to SSI_FS output invalid
-2
ns
S7
SSI_BCLK to SSI_TXD valid
15
ns
S8
SSI_BCLK to SSI_TXD invalid / high impedence
-4
ns
S9
SSI_RXD / SSI_FS input setup before SSI_BCLK
15
ns
S10
SSI_RXD / SSI_FS input hold after SSI_BCLK
0
ns
Table 15. SSI Timing – Slave Modes1
1 All timings specified with a capactive load of 25pF.
Num
Description
Symbol
Min
Max
Units
S11
SSI_BCLK cycle time
tBCLK
8
× t
SYS
—ns
S12
SSI_BCLK pulse width high/low
45%
55%
tBCLK
S13
SSI_FS input setup before SSI_BCLK
10
ns
S14
SSI_FS input hold after SSI_BCLK
3
ns
S15
SSI_BCLK to SSI_TXD/SSI_FS output valid
15
ns
S16
SSI_BCLK to SSI_TXD/SSI_FS output invalid/high
impedence
-2
ns
S17
SSI_RXD setup before SSI_BCLK
10
ns
S18
SSI_RXD hold after SSI_BCLK
3
ns
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MCF53721CVM240,
MCF5372LCVM240,
MCF5373LCVM240
相關(guān)PDF資料
PDF描述
MCF53721CVM240 32-BIT, 240 MHz, RISC PROCESSOR, PBGA196
MCF5373CAB180 32-BIT, 180 MHz, RISC PROCESSOR, PQFP160
MCF5372LCVM240 32-BIT, 240 MHz, RISC PROCESSOR, PBGA196
MCF5407FT162 32-BIT, 162 MHz, RISC PROCESSOR, PQFP208
MCF5407FT220 32-BIT, 220 MHz, RISC PROCESSOR, PQFP208
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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