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參數(shù)資料
型號(hào): MCF5275CVM166
廠商: Freescale Semiconductor
文件頁數(shù): 32/44頁
文件大?。?/td> 0K
描述: IC MCU 32BIT 166MHZ 256-MAPBGA
標(biāo)準(zhǔn)包裝: 90
系列: MCF527x
核心處理器: Coldfire V2
芯體尺寸: 32-位
速度: 166MHz
連通性: EBI/EMI,以太網(wǎng),I²C,SPI,UART/USART,USB
外圍設(shè)備: DMA,WDT
輸入/輸出數(shù): 69
程序存儲(chǔ)器類型: ROMless
RAM 容量: 64K x 8
電壓 - 電源 (Vcc/Vdd): 1.4 V ~ 1.6 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 256-LBGA
包裝: 散裝
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4
Electrical Characteristics
Freescale Semiconductor
38
8.12
I2C Input/Output Timing Specifications
Table 23 lists specifications for the I2C input timing parameters shown in Figure 21.
Table 24 lists specifications for the I2C output timing parameters shown in Figure 21.
Table 23. I2C Input Timing Specifications between I2C_SCL and I2C_SDA
Num
Characteristic
Min
Max
Units
I1
Start condition hold time
2 x tCYC
—ns
I2
Clock low period
8 x tCYC
—ns
I3
I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V)
1
ms
I4
Data hold time
0
ns
I5
I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V)
1
ms
I6
Clock high time
4 x tCYC
—ns
I7
Data setup time
0
ns
I8
Start condition setup time (for repeated start condition only)
2 x tCYC
—ns
I9
Stop condition setup time
2 x tCYC
—ns
Table 24. I2C Output Timing Specifications between I2C_SCL and I2C_SDA
Num
Characteristic
Min
Max
Units
I11
1
Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the
maximum frequency (IFDR = 0x20) results in minimum output timings as shown in Table 24. The
I2C interface is designed to scale the actual data transition time to move it to the middle of the
I2C_SCL low period. The actual position is affected by the prescale and division values
programmed into the IFDR; however, the numbers given in Table 24 are minimum values.
Start condition hold time
6 x tCYC
—ns
I2 1
Clock low period
10 x tCYC
—ns
I3 2
2
Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only
actively drive low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external
signal capacitance and pull-up resistor values.
I2C_SCL/I2C_SDA rise time
(VIL = 0.5 V to VIH = 2.4 V)
——
s
I4 1
Data hold time
7 x tCYC
—ns
I5 3
3
Specified at a nominal 50-pF load.
I2C_SCL/I2C_SDA fall time
(VIH = 2.4 V to VIL = 0.5 V)
—3
ns
I6 1
Clock high time
10 x tCYC
—ns
I7 1
Data setup time
2 x tCYC
—ns
I8 1
Start condition setup time (for repeated start
condition only)
20 x tCYC
—ns
I9 1
Stop condition setup time
10 x tCYC
—ns
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