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Physical Layer Interface Controller (PLIC)
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
13-30
Freescale Semiconductor
13.5.18 GCI C/I Channel Transmit Status Register (PGCITSR)
All bits in this register are read only and are cleared on hardware or software reset.
The PGCITSR register is an 8-bit register containing the C/I channel status bits for each of the four
transmit ports on the MCF5272.
7
4
3
210
Field
—
ACK3
ACK2
ACK1
ACK0
Reset
0000_0000
R/W
Read Only
Addr
MBAR + 0x37F
Figure 13-30. GCI C/I Channel Transmit Status Register (PGCITSR)
Table 13-13. PGCITSR Field Descriptions
Bits
Name
Description
7–4
—
Reserved, should be cleared.
3
ACK3
Acknowledge, port 3.
0 Default reset value.
1 Set by the C/I channel controller to indicate that the previous C/I data has been transmitted in
two successive C/I words. The ACK bit is automatically cleared by the CPU when the PGCITSR
register has been read.
2
ACK2
Acknowledge, port 2. See ACK3.
1
ACK1
Acknowledge, port 1. See ACK3.
0
ACK0
Acknowledge, port 0. See ACK3.