參數(shù)資料
型號(hào): MCF52100CAE66
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 14/56頁(yè)
文件大小: 0K
描述: IC MCU 64K FLASH 66MHZ 64LQFP
標(biāo)準(zhǔn)包裝: 160
系列: MCF521xx
核心處理器: Coldfire V2
芯體尺寸: 32-位
速度: 66MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: DMA,LVD,POR,PWM,WDT
輸入/輸出數(shù): 43
程序存儲(chǔ)器容量: 64KB(64K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-LQFP
包裝: 托盤
配用: M5211DEMO-ND - KIT DEMO FOR MCF5211
Family Configurations
MCF52110 ColdFire Microcontroller, Rev. 1
Freescale Semiconductor
21
1.6
External Interrupt Signals
Table 8 describes the external interrupt signals.
1.7
Queued Serial Peripheral Interface (QSPI)
Table 9 describes the QSPI signals.
1.8
I2C I/O Signals
Table 10 describes the I2C serial interface module signals.
1 The PLL pre-divider (CCHR+1) reset value is 1 and the PLL input reference range is 2–10 MHz,
so in order to boot with the PLL enabled, the external clock or crystal frequency needs to be less
than 10 MHz. MCF5211x devices cannot boot with PLL enabled from an external clock or
crystal oscillator with frequency greater than 10 MHz. This constraint does not apply to booting
with PLL disabled.
2 Cannot boot from the Internal 8 MHz Relaxation oscillator with the PLL enabled. Refer Note1.
Thus this mode has been removed from the table.
Table 8. External Interrupt Signals
Signal Name
Abbreviation
Function
I/O
External Interrupts
IRQ[7:1]
External interrupt sources.
I
Table 9. Queued Serial Peripheral Interface (QSPI) Signals
Signal Name
Abbreviation
Function
I/O
QSPI Synchronous
Serial Output
QSPI_DOUT Provides the serial data from the QSPI and can be programmed to be
driven on the rising or falling edge of QSPI_CLK.
O
QSPI Synchronous
Serial Data Input
QSPI_DIN
Provides the serial data to the QSPI and can be programmed to be
sampled on the rising or falling edge of QSPI_CLK.
I
QSPI Serial Clock
QSPI_CLK
Provides the serial clock from the QSPI. The polarity and phase of
QSPI_CLK are programmable.
O
Synchronous Peripheral
Chip Selects
QSPI_CS[3:0] QSPI peripheral chip select; can be programmed to be active high or
low.
O
Table 10. I2C I/O Signals
Signal Name
Abbreviation
Function
I/O
Serial Clock
SCLn
Open-drain clock signal for the for the I2C interface. When the bus is
In master mode, this clock is driven by the I2C module; when the bus
is in slave mode, this clock becomes the clock input.
I/O
Serial Data
SDAn
Open-drain signal that serves as the data input/output for the I2C
interface.
I/O
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