LIST OF ILLUSTRATIONS (Continued)
Figure
Page
Number
Title
Number
xviii
MCF5206 USERS MANUAL Rev 1.0
MOTOROLA
10-4.
Connection Diagram for 1MByte DRAM with 8-bit Port and 1 KByte Page . 10-15
10-5.
Byte Read Transfers in Normal Mode with 8-bit DRAM ............................... 10-17
10-6.
Longword Write Transfer in Normal Mode with 16-bit DRAM ...................... 10-19
10-7.
Word Write Transfer in Fast Page Mode with 8-bit DRAM .......................... 10-22
10-8.
Longword Read Transfer Followed by a Page Hit Longword Read Transfer in Fast
Page Mode with 32-bit DRAM ...................................................................... 10-24
10-9.
Word Write Transfer Followed by a Page Hit Word Write Transfer in Fast Page Mode
with 16-bit DRAM ......................................................................................... 10-26
10-10. Byte Read Transfer Followed by a Page Miss Byte Read Transfer in Fast Page Mode
with 8-bit DRAM ........................................................................................... 10-28
10-11. Bus Arbitration in Fast Page Mode .............................................................. 10-31
10-12. Longword Write Transfer Followed by a Word Read Transfer in Burst Page Mode
with 16-bit DRAM ......................................................................................... 10-33
10-13. Word Read Transfer Followed by a Page Miss Byte Read Transfer in Fast Page
Mode with 8-bit EDO DRAM ........................................................................ 10-36
10-14. Alternate Master Byte Read Transfer Followed by Byte Write Transfer in Normal
Mode with 16-bit DRAM ............................................................................... 10-42
10-15. Alternate Master Longword Write Transfer in Normal Mode with 16-bit DRAM
...................................................................................................................... 10-45
10-16. Alternate Master Word Read Transfer in Burst Page Mode with 8-bit DRAM
...................................................................................................................... 10-48
10-17. Normal Mode DRAM Transfer Timing .......................................................... 10-54
10-18. Fast Page Mode or Burst Page Mode DRAM Transfer Timing .................... 10-54
10-19. Fast Page Mode or Burst Page Mode DRAM Transfer Timing .................... 10-55
10-20. Fast Page Mode Page Hit and Page Miss DRAM Transfer Timing ............. 10-56
10-21. Fast Page Mode or Burst Page Mode EDO DRAM Transfer Timing ........... 10-57
10-22. CAS before RAS Refresh Cycle Timing ....................................................... 10-58
11-1.
UART Block Diagram...................................................................................... 11-1
11-2.
External and Internal Interface Signals ........................................................... 11-4
11-3.
Baud-Rate Timer Generator Diagram............................................................. 11-5
11-4.
Transmitter and Receiver Functional Diagram ............................................... 11-7
11-5.
Transmitter Timing Diagram ........................................................................... 11-8
11-6.
Receiver Timing Diagram ............................................................................. 11-10
11-7.
Looping Modes Functional Diagram ............................................................. 11-13
11-8.
Multidrop Mode Timing Diagram................................................................... 11-15
11-9.
UART Software Flowchart ............................................................................ 11-35
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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