參數資料
型號： MCF51JE256VML
廠商： Freescale Semiconductor
文件頁數： 24/47頁
文件大?。?/td> 0K
描述： IC MCU 256K COLDF 104-PBGA
標準包裝： 240
系列： MCF51JE
核心處理器： Coldfire V1
芯體尺寸： 32-位
速度： 50MHz
連通性： CAN，EBI/EMI，I²C，SCI，SPI，USB OTG
外圍設備： LVD，PWM，WDT
輸入/輸出數： 69
程序存儲器容量： 256KB（256K x 8）
程序存儲器類型： 閃存
RAM 容量： 32K x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 3.6 V
數據轉換器： A/D 12x12b，D/A 1x12b
振蕩器型： 外部
工作溫度： -40°C ~ 105°C
封裝/外殼： 104-LFBGA
包裝： 管件
MCF51JE256 Datasheet, Rev. 4
Preliminary Electrical Characteristics
Freescale Semiconductor
30
5
Total deviation of trimmed DCO
output frequency over voltage and
temperature
over voltage and
temperature
f
dco_t
—
1.0
2
%fdco
P
over fixed voltage
and temp range
of 0 - 70
C
—
0.5
1
%fdco
C
6
Acquisition time
FLL2
tfll_acquire
——
1
ms
C
PLL3
tpll_acquire
——
1
ms
D
7
Long term Jitter of DCO output clock (averaged over 2mS
interval) 4
CJitter
—
0.02
0.2
%fdco
C
8
VCO operating frequency
fvco
7.0
—
55.0
MHz
D
9
PLL reference frequency range
fpll_ref
1.0
—
2.0
MHz
D
10
Jitter of PLL output clock measured
over 625 ns
Long term
fpll_jitter_625
ns
—
0.5664
—%fpll
D
11 Lock frequency tolerance
Entry5
Dlock
1.49
—
2.98
%
D
Exit6
Dunl
4.47
—
5.97
%
D
12 Lock time
FLL
tfll_lock
——
tfll_acquire+
1075(1/fint_t)
sD
PLL
tpll_lock
——
tpll_acquire+
1075(1/fpll_ref)
sD
13 Loss of external clock minimum frequency - RANGE = 0
floc_low
(3/5) x
fint_t
—
kHz
D
14 Loss of external clock minimum frequency - RANGE = 1
floc_high
(16/5) x
fint_t
——
kHz
D
1
This should not exceed the maximum CPU frequency of 50.33 MHz.
2
This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is
changed, DRS bit is changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is
being used as the reference, this specification assumes it is already running.
3
This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI)
to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
4
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBUS. Measurements are
made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via
VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a given interval.
5
Below Dlock minimum, the MCG is guaranteed to enter lock. Above Dlock maximum, the MCG will not enter lock. But if the MCG is already
in lock, then the MCG may stay in lock.
6
Below Dunl minimum, the MCG will not exit lock if already in lock. Above Dunl maximum, the MCG is guaranteed to exit lock.
Table 17. MCG (Temperature Range = –40 to 105
C Ambient) (continued)
#
Rating
Symbol
Min
Typical
Max
Unit
C
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