
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2)
MC9S12XE-Family Reference Manual , Rev. 1.13
Freescale Semiconductor
1227
29.3.2.1
Flash Clock Divider Register (FCLKDIV)
The FCLKDIV register is used to control timed events in program and erase algorithms.
All bits in the FCLKDIV register are readable, bits 6–0 are write once and bit 7 is not writable .
0x000C
ETAGHI
R
ETAG15
ETAG14
ETAG13
ETAG12
ETAG11
ETAG10
ETAG9
ETAG8
W
0x000D
ETAGLO
R
ETAG7
ETAG6
ETAG5
ETAG4
ETAG3
ETAG2
ETAG1
ETAG0
W
0x000E
FECCRHI
R
ECCR15
ECCR14
ECCR13
ECCR12
ECCR11
ECCR10
ECCR9
ECCR8
W
0x000F
FECCRLO
R
ECCR7
ECCR6
ECCR5
ECCR4
ECCR3
ECCR2
ECCR1
ECCR0
W
0x0010
FOPT
R
NV7
NV6
NV5
NV4
NV3
NV2
NV1
NV0
W
0x0011
FRSV0
R
0
00000
W
0x0012
FRSV1
R
0
00000
W
0x0013
FRSV2
R
0
00000
W
= Unimplemented or Reserved
Offset Module Base + 0x0000
76543210
R
FDIVLD
FDIV[6:0]
W
Reset
00000000
= Unimplemented or Reserved
Figure 29-5. Flash Clock Divider Register (FCLKDIV)
Address
& Name
7
6
5
4
3210
Figure 29-4. FTM1024K5 Register Summary (continued)