
Appendix A Electrical Characteristics
MC9S12XDP512 Data Sheet, Rev. 2.21
1276
Freescale Semiconductor
In
Table A-26 the timing characteristics for master mode are listed.
Figure A-8.
Derating of maximum fSCK to fbus ratio in Master Mode
In Master Mode the allowed maximum fSCK to fbus ratio (= minimum Baud Rate Divisor, pls. see
SPI Section) derates with increasing fbus.
A.7.2
Slave Mode
In
Figure A-9 the timing diagram for slave mode with transmission format CPHA = 0 is depicted.
Table A-26. SPI Master Mode Timing Characteristics
Num
C
Characteristic
Symbol
Min
Typ
Max
Unit
1
D
SCK frequency
fsck
1/2048
—
1
/2fbus
1
D
SCK period
tsck
2
—
2048
tbus
2
D
Enable lead time
tlead
—
1/2
—
tsck
3
D
Enable lag time
tlag
—
1/2
—
tsck
4
D
Clock (SCK) high or low time
twsck
—
1/2
—
tsck
5
D
Data setup time (inputs)
tsu
8—
—
ns
6
D
Data hold time (inputs)
thi
8—
—
ns
9
D
Data valid after SCK edge
tvsck
—
15
ns
10
D
Data valid after SS fall (CPHA = 0)
tvss
—
15
ns
11
D
Data hold time (outputs)
tho
0—
—
ns
12
D
Rise and fall time inputs
tr
——
8
ns
13
D
Rise and fall time outputs
trfo
——
8
ns
1/2
1/4
fSCK/fbus
fbus [MHz]
10
20
30
40
15
25
35
5