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Chapter 12 Serial Peripheral Interface (SPIV3) Block Description
MC9S12KT256 Data Sheet, Rev. 1.16
410
Freescale Semiconductor
12.3.2.4
SPI Status Register (SPISR)
Read: anytime
Write: has no effect
12.3.2.5
SPI Data Register (SPIDR)
Read: anytime; normally read only after SPIF is set
Module Base 0x0003
76543210
R
SPIF
0
SPTEF
MODF
0000
W
Reset
0
1
00000
= Unimplemented or Reserved
Figure 12-6. SPI Status Register (SPISR)
Table 12-8. SPISR Field Descriptions
Field
Description
7
SPIF
SPIF Interrupt Flag — This bit is set after a received data byte has been transferred into the SPI Data Register.
This bit is cleared by reading the SPISR register (with SPIF set) followed by a read access to the SPI Data
Register.
0 Transfer not yet complete
1 New data copied to SPIDR
5
SPTEF
SPI Transmit Empty Interrupt Flag — If set, this bit indicates that the transmit data register is empty. To clear
this bit and place data into the transmit data register, SPISR has to be read with SPTEF = 1, followed by a write
to SPIDR. Any write to the SPI Data Register without reading SPTEF = 1, is effectively ignored.
0 SPI Data register not empty
1 SPI Data register empty
4
MODF
Mode Fault Flag — This bit is set if the SS input becomes low while the SPI is congured as a master and mode
fault detection is enabled, MODFEN bit of SPICR2 register is set. Refer to MODFEN bit description in
Register (with MODF set) followed by a write to the SPI Control Register 1.
0 Mode fault has not occurred.
1 Mode fault has occurred.
Module Base 0x0005
76543210
R
Bit 7
6
5
4322
Bit 0
W
Reset
0
00000
= Unimplemented or Reserved
Figure 12-7. SPI Data Register (SPIDR)